Time-Domain Simulation of Variational Interconnect Models

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E. Acar, S. Nassif and L. Pileggi, “Time-Domain Simulation of Variational Interconnect Models”, Int’l Symposium on Quality in Electronic Design, March 2002.

False coupling interactions in static timing analysis

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R. Arunachalam, R. D. Blanton and L. Pileggi, “False coupling interactions in static timing analysis”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.

Inductance 101 (Embedded Tutorial)

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M. Beattie, L. Pileggi, “Inductance 101 (Embedded Tutorial)”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.

Modeling Magnetic Coupling for Gigascale Interconnect

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M. Beattie, L. Pileggi, “Modeling Magnetic Coupling for Gigascale Interconnect”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.

Min/Max On-Chip Inductance Models and Delay Metrics

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Y-C. Lu, M. Celik, T. Young, and L. Pileggi, “Min/Max On-Chip Inductance Models and Delay Metrics”, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.

Overcoming Wireload Model Uncertainty During Physical Design

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P. Gopalakrishnan, A. Odabasioglu, L. Pileggi and S. Raje, “Overcoming Wireload Model Uncertainty During Physical Design”, Int’l Symposium on Physical Design (ISPD), April 2001.

RC(L)Interconnect Sizing With Second Order Considerations via Posynomial Programming

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T. Lin and L. Pileggi, “RC(L)Interconnect Sizing With Second Order Considerations via Posynomial Programming”, Int’l Symposium on Physical Design (ISPD), April 2001.

Efficient Inductance Extraction via Windowing

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M. Beattie and L. Pileggi, “Efficient Inductance Extraction via Windowing”, Design and Test in Europe Conference (DATE), March 2001.

Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations

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E. Acar, S. Nassif and L. Pileggi, Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations, Int’l Symposium on Quality in Electronic Design, March 2001.

Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations

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E. Acar, S. Nassif and L. Pileggi, “Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations”, ACM/IEEE Workshop on Timing in the Specification and Synthesis of Digital Systems, December 2000.