RC(L) Interconnect Sizing with Second Order Considerations
T. Lin and L. Pileggi, “RC(L) Interconnect Sizing with Second Order Considerations”, Proceedings of the SRC Techcon Conference, September 2000.
This author has yet to write their bio.Meanwhile lets just say that we are proud awp contributed a whooping 431 entries.
T. Lin and L. Pileggi, “RC(L) Interconnect Sizing with Second Order Considerations”, Proceedings of the SRC Techcon Conference, September 2000.
R. Arunachalam and L.T. Pileggi, “Can We Continue to Predict Timing of ICs Prior to Manufacturing as Technologies Continue to Scale?”, ISD Magazine, September 2000.
Y. Liu, S. Nassif, L. Pileggi and A.J. Strojwas, “Impact of interconnect variations on the clock skew of a gigahertz microprocessor”, Proceedings of the Design Automation Conference, June 2000.
R. Arunachalam, K. Rajagopal and L. Pileggi, “TACO: Timing Analysis with Coupling”, Proceedings of the Design Automation Conference, June 2000.
A. Odabasioglu, M. Celik & L. T. Pileggi, “Practical Considerations for Passive Reduction of RLC Circuits”, Proceedings of the International Conference on Computer- Aided Design, November 1999.
M. Beattie and L. Pileggi, “Electromagnetic Parasitic Extraction via a Multipole Method with Hierarchical Refinement”, Proceedings of the International Conference on Computer-Aided Design, November 1999.
A. Odabasioglu, M. Celik & L. T. Pileggi, “Efficient and Accurate Delay Metrics for RC Interconnect”, PATMOS: International Workshop on Power and Timing Modeling, Optimization and Simulation, October 1999.
M. Beattie and L. Pileggi, “IC Analyses Including Extracted Inductance Models”, Proceedings of the Design Automation Conference, Invited Paper, June 1999.
Y. Liu, L. Pileggi and A.J. Strojwas, “Model Order-Reduction of RC(L) Interconnect including Variational Analysis”, Proceedings of the Design Automation Conference (Best Paper Award Nomination), June 1999.
E. Acar, A. Odabasioglu, M. Celik and L. Pileggi, “S2P: Stable 2-Pole Model for RC Interconnect Delay Analysis”, Proceedings of the 9th Great Lakes Symposium on VLSI, March 1999.
Carnegie Mellon University
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pileggi@andrew.cmu.edu
Phone: 412-268-6774