Modeling Nonlinear Communication ICs Using a Multivariate Formulation
P. Li and L. Pileggi, “Modeling Nonlinear Communication ICs Using a Multivariate Formulation”, IEEE International Workshop on Behavioral Modeling and Simulation, October 2003.
Author Archive for: awp
Entries by awp
A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits
P. Li, X. Li, Y. Xu and L. Pileggi, “A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits”, Proceedings of the International Conference on Computer-Aided Design, November 2003.
Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics
J. Le, A. Devgan and L. Pileggi, “Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics”, Proceedings of the International Conference on Computer-Aided Design, November 2003.
On-Package Decoupling Optimization with Package Macromodels
H. Zheng, B. Krauter, L. Pileggi, “On-Package Decoupling Optimization with Package Macromodels”, Int’l Custom Integrated Circuits Conference, Sept. 2003.
Regular Logic Fabrics for a Via Patterned Gate Array (VPGA)
K.Y. Tong, V. Kheterapal, S. Rovner, H. Schmit, L. Pileggi, R. Puri, “Regular Logic Fabrics for a Via Patterned Gate Array (VPGA)”, Int’l Custom Integrated Circuits Conference, Sept. 2003.
Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics
A. Koorapaty, L. Pileggi, H. Schmit, “Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics”, International Conference on Field Programmable Logic and Applications, September 2003.
Hierarchical Modeling of Electrostatic and Magnetostatic Coupling
S. Gupta and L. Pileggi, “Hierarchical Modeling of Electrostatic and Magnetostatic Coupling”, Proceedings of the SRC Techcon Conference, August 2003.
Simulation Approach for Inductance Effects of VLSI Interconnects
X. Qi, G. Leonhardt, D. Flees, X-D, Yang, S. Kim, S. Mueller, H. Mau and L. Pileggi, “Simulation Approach for Inductance Effects of VLSI Interconnects”, In Proc. of the Great Lakes Symposium on VLSI, May 2003.
Bounding the Efforts on Congestion Optimization for Physical Synthesis
D. Pandini, L. Pileggi, A. Strojwas, “Bounding the Efforts on Congestion Optimization for Physical Synthesis”, In Proc. of the Great Lakes Symposium on VLSI, May 2003.
Cheap and Under Control: The Next Implementation Fabric
I. Bolsens, A. Broom, C. Hamlin, P. Magarshack, Z. Or-Bach and L. Pileggi, Fast, “Cheap and Under Control: The Next Implementation Fabric”, IEEE/ACM Design Automation Conference, June 2003.
