L.T. Pillage and R.A. Rohrer, “Delay Evaluation with Lumped Linear RLC Interconnect Circuit Models”, Proceedings Decennial Caltech Conference on VLSI, March 1989.
http://users.ece.cmu.edu/~pileggi/wp-content/uploads/2020/05/CMU-logo-v4.png00awphttp://users.ece.cmu.edu/~pileggi/wp-content/uploads/2020/05/CMU-logo-v4.pngawp1989-03-01 08:00:002018-06-28 16:25:21Delay Evaluation with Lumped Linear RLC Interconnect Circuit Models
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