I. Tesu and L. Pileggi, “Timing Analysis Models for Gates and Cells with Bipolar Transistor Output Stages”, Proceedings of the IEEE ASIC Conference, 1995.
http://users.ece.cmu.edu/~pileggi/wp-content/uploads/2020/05/CMU-logo-v4.png00awphttp://users.ece.cmu.edu/~pileggi/wp-content/uploads/2020/05/CMU-logo-v4.pngawp1995-10-01 08:00:002018-06-28 16:19:01Timing Analysis Models for Gates and Cells with Bipolar Transistor Output Stages
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