Time-Domain Simulation of Variational Interconnect Models
E. Acar, S. Nassif and L. Pileggi, “Time-Domain Simulation of Variational Interconnect Models”, Int’l Symposium on Quality in Electronic Design, March 2002.
Archive for month: March, 2002
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpH. Zhang, B. Krauter, M. Beattie and L. Pileggi, “Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses”, Design and Test in Europe Conference (DATE), March 2002.
A Linear-Centric Simulation Framework for Parametric Fluctuations
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpE. Acar, L. Pileggi and S. Nassif, “A Linear-Centric Simulation Framework for Parametric Fluctuations”, Design and Test in Europe Conference (DATE), March 2002.
On-Chip Inductance Models:3D or not 3D?
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpT. Lin, M. Beattie and L. Pileggi, “On-Chip Inductance Models:3D or not 3D?”, Design and Test in Europe Conference (DATE), March 2002.
A Linear-Centric Modeling Approach to Harmonic Balance Analysis
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpP. Li and L. Pileggi, “A Linear-Centric Modeling Approach to Harmonic Balance Analysis”, Design and Test in Europe Conference (DATE), March 2002.
Congestion-Aware Logic Synthesis
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpD. Pandini, L. Pileggi and A. Strojwas, “Congestion-Aware Logic Synthesis”, Design and Test in Europe Conference (DATE), March 2002.
Contact
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5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774