Introduction The continuous drive towards smaller feature size, larger die, and higher clock frequency has lead to a significant increase in fabrication cost. In addition, decrease in life cycle of most IC products makes rapid yield learning more crucial than ever to ensure the economic succcess of the product. Further, if the yield of a design can be estimated ahead of the time before committing manufacturing resource, corrections can be made to improve yield. The manufacturer may benefit from significant savings in both time-to-market and manufacturing cost. To achieve yield prediction and rapid yield learning requires knowledge about the underlying nature of the faults, which can be learned by physically analyzing the chip. However, this method is both time-consuming and costly. Another way to solve this problem is through simulation For this purpose, we conducted a research to explore the relationsip between contamination, defect and fault. This lead to the development of the Contamination-Defect- Fault Simulator (CODEF). The purpose of this web page is to provide the status of this research project. This web page includes the evolution of the simulator. It contains some past experimental results as well as future research goals. Publications relating to the simulator can also be found here.

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