Stack Computers: the new wave
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All Rights Reserved.
Current Stack Hardware
Currently Available Forth/Stack Hardware
- Ultra Technology including
information on several stack CPU chips, including:
- MuP21 -- minimalist
21-bit processor (designed by Chuck Moore)
- F21 -- follow-on chip
to MuP21 (designed by Chuck Moore)
- Patriot Scientific sells the
PSC1000 (shBoom) as a Java
processor (originally designed by Chuck Moore, with many additional features by
George Shaw (and others?))
- MPE sells
RTX 2000 systems
- The Novix NC4016 was designed by Chuck Moore
with Bob Murphy "driving" CAD tools, and input from Greg Bailey and
- The RTX 2000 was based on a next-generation Novix
design which was sold to Harris, with the Novix design improvements made by
John Rible and Bob Murphy.
John Rible writes: "I apologize for the 2 carry bits: I initially let Bob
convince me it was the best way, and then couldn't get Harris to accept my fix
a month after we transferred the design. sigh."
- Silicon Composers offers:
- The SC32 chip (designed by John Hayes & Marty
Fraeman at JHU/APL).
- RTX 2000 systems
- SandPiper Technology makes the
BRISC CPU as a soft-core design in Verilog (John Rible:
- 16-bit FPGA of QS3 being used at UCSC for an extension class
- 32-bit QS2
- They offer relatively low-cost hardware to explore the technology
- Mountain View Press offers:
- WISC CPU/16 discrete logic CPU (design by Phil
- WISC CPU/32 CPU with close cousins Harris RTX-32P
and BINAR stack CPU chips (designs by Phil Koopman)
- New Micros sells the F68HC11, which
is a register-based CPU with Forth in masked ROM, in addition to a selection of
related harware and software.
- FirmWorks supports the IEEE Std
1275-1994 Open Firmware,
which uses a stack-based abstract execution architecture.
- RTX 2000 die photo
The two rectangles at the bottom left and right are the return stack and data
stack. The hardware multiplier and all the other gates are implemented as
standard cells in the larger irregularly filled area. Pads for pins are around
- RTX 32P: data chip die
photo| control chip
These are the chip implementation of the RTX-32P, which is essentially
identical in design to the LSI chip implementation of the WISC CPU/32. This was
a two-chip implementation because of the limited space on 2.5 micron standard
cell. The large rectangular areas are data stack and microcode memory (data
chip); return stack and microcode memory (control chip). The microcode memory
was entirely in RAM, and the stack sizes were large, leading to most of the
chip space being used for memory. Yield was moderate, but a number of 100% good
die were produced and worked at about 8 MHz.
- BINAR: layout |
The BINAR chip was a refined version of the RTX 32P. It was optimized for CMOS
instead of TTL discrete logic, and had some architectural improvements such as
a packed instruction word that had 2 instructions per 32-bit words to improve
code density and execution speed (it could retire 2 stack instructions every
main memory cycle). I don't have a good die photo, but my 1200 dpi scanner did
an OK job of imaging a packaged chip. The square areas at the bottom left and
right are the data stack and return stack. The square areas at the top are
microcode RAM and ROM (most instructions were in ROM, but a few instructions
could be added by the user in the RAM area, which is the larger area to the
left. Note that RAM is about 8x bigger than ROM per bit stored in that
technology). The stuff in between is standard cell logic arranged in rows
across the chip. "BINAR" stands for "Binar Is Not An RTX"
because we were prohibited from calling it an RTX chip since it was a prototype
and not a product. Yield was quite good and a number of working chips were
produced typically running at 16 MHz on a 2.5 micron standard cell process
(with a gate library tweaked to be closer to 2.0 microns).
- Harold Rabbie (email@example.com) points out that the Motorola 6809
had, unlike the 6800, two stack registers that could be used to implement an
efficient Forth interpreter.
- I note from my own experience that the 6502 microprocessor also had two
index registers that were useful for Forth interpreters. But, it didn't have
addressing modes that automatically adjusted the pointers for "push"
and "pop" operations.
Starting point for other Stack & Forth information:
Phil Koopman --