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fpga_architecture_for_computing [2022/08/20 11:15] – [Students] editfpga_architecture_for_computing [2023/02/03 13:15] (current) – [Students] edit
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     * Shashank Obla     * Shashank Obla
     * Siddharth Sahay     * Siddharth Sahay
 +    * Eric Tang
     * Chengyue Wang     * Chengyue Wang
   * Past   * Past
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   * Our initial concept is based on factoring out the concerns for data orchestration from the compute kernels. The in-fabric computation kernels interacting with only the simple on-chip SRAM blocks for data input and output ([[https://users.ece.cmu.edu/~jhoe/distribution/2011/fpga11.pdf |Chung, FPGA'2011]]). Separately, a set of control threads—expressed in a multithreaded C-like language—manage (1) the data movements between the off-chip DRAM and on-chip SRAMs, and also (2) the invocations of the kernels over time.  The CoRAM compiler automatically infers and synthesizes from the control threads both the required data transfer paths and the state-machine controllers in support of the computation kernels.    * Our initial concept is based on factoring out the concerns for data orchestration from the compute kernels. The in-fabric computation kernels interacting with only the simple on-chip SRAM blocks for data input and output ([[https://users.ece.cmu.edu/~jhoe/distribution/2011/fpga11.pdf |Chung, FPGA'2011]]). Separately, a set of control threads—expressed in a multithreaded C-like language—manage (1) the data movements between the off-chip DRAM and on-chip SRAMs, and also (2) the invocations of the kernels over time.  The CoRAM compiler automatically infers and synthesizes from the control threads both the required data transfer paths and the state-machine controllers in support of the computation kernels. 
   * We later introduced a soft-logic CoRAM abstraction layer with further elevated kernel and control thread application-level interfaces that directly support the high-level semantics of commonly-used in-memory data structure types (e.g., streams, arrays, linked lists, and trees) ([[https://users.ece.cmu.edu/~jhoe/distribution/2015/fpl2015.pdf |Weisz, FPL'2015]]).     * We later introduced a soft-logic CoRAM abstraction layer with further elevated kernel and control thread application-level interfaces that directly support the high-level semantics of commonly-used in-memory data structure types (e.g., streams, arrays, linked lists, and trees) ([[https://users.ece.cmu.edu/~jhoe/distribution/2015/fpl2015.pdf |Weisz, FPL'2015]]).  
-  * We developed the [[https://research.ece.cmu.edu/calcm/new_connect/connect/  |CONNECT NoC Generator]] in support of CoRAM.+  * We developed the [[https://github.com/crossroadsfpga/connect  |CONNECT NoC Generator]] in support of CoRAM.
          
  
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     * [[http://research.ece.cmu.edu/~coram/doku.php?id=corflow_beta |CoRAM-classic demo and downloads]]     * [[http://research.ece.cmu.edu/~coram/doku.php?id=corflow_beta |CoRAM-classic demo and downloads]]
     * [[http://research.ece.cmu.edu/~coram/doku.php?id=fpga_2013_tutorial | CoRAM-classic Tutorial at FPGA-2013]]     * [[http://research.ece.cmu.edu/~coram/doku.php?id=fpga_2013_tutorial | CoRAM-classic Tutorial at FPGA-2013]]
-    * [[http://research.ece.cmu.edu/calcm/connect |CONNECT NoC Generator]]+    * [[https://github.com/crossroadsfpga/connect |CONNECT NoC Generator]]
     * [[http://research.ece.cmu.edu/calcm/connect_hls |CONNECT NoC in Vivado-HLS synthesizable C]]     * [[http://research.ece.cmu.edu/calcm/connect_hls |CONNECT NoC in Vivado-HLS synthesizable C]]