Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
Next revisionBoth sides next revision
fpga_architecture_for_computing [2020/11/26 22:54] – [Network Function Acceleration] editfpga_architecture_for_computing [2021/02/05 13:45] – [CoRAM (Classic)] edit
Line 5: Line 5:
 Funding for this work has been provided, in part, by the National Science Foundation (CCF-1012851), Intel ISRA, and SRC/JUMP. We thank Altera, Xilinx and Bluespec for their donation of tools and hardware.  Funding for this work has been provided, in part, by the National Science Foundation (CCF-1012851), Intel ISRA, and SRC/JUMP. We thank Altera, Xilinx and Bluespec for their donation of tools and hardware. 
  
 +Please follow continuing developments at the [[https://www.nexusfpga.org |Nexus FPGA Research Center]] jointly supported by Intel and VMware.
 =====Students===== =====Students=====
     * Eric Chung ([[http://www.ece.cmu.edu/~jhoe/distribution/2011/chung.pdf |PhD Thesis]], 2011)     * Eric Chung ([[http://www.ece.cmu.edu/~jhoe/distribution/2011/chung.pdf |PhD Thesis]], 2011)
Line 53: Line 54:
   * Our initial concept is based on factoring out the concerns for data orchestration from the compute kernels. The in-fabric computation kernels interacting with only the simple on-chip SRAM blocks for data input and output ([[http://www.ece.cmu.edu/~jhoe/distribution/2011/fpga11.pdf |Chung, FPGA'2011]]). Separately, a set of control threads—expressed in a multithreaded C-like language—manage (1) the data movements between the off-chip DRAM and on-chip SRAMs, and also (2) the invocations of the kernels over time.  The CoRAM compiler automatically infers and synthesizes from the control threads both the required data transfer paths and the state-machine controllers in support of the computation kernels.    * Our initial concept is based on factoring out the concerns for data orchestration from the compute kernels. The in-fabric computation kernels interacting with only the simple on-chip SRAM blocks for data input and output ([[http://www.ece.cmu.edu/~jhoe/distribution/2011/fpga11.pdf |Chung, FPGA'2011]]). Separately, a set of control threads—expressed in a multithreaded C-like language—manage (1) the data movements between the off-chip DRAM and on-chip SRAMs, and also (2) the invocations of the kernels over time.  The CoRAM compiler automatically infers and synthesizes from the control threads both the required data transfer paths and the state-machine controllers in support of the computation kernels. 
   * We later introduced a soft-logic CoRAM abstraction layer with further elevated kernel and control thread application-level interfaces that directly support the high-level semantics of commonly-used in-memory data structure types (e.g., streams, arrays, linked lists, and trees) ([[http://www.ece.cmu.edu/~jhoe/distribution/2015/fpl2015.pdf |Weisz, FPL'2015]]).     * We later introduced a soft-logic CoRAM abstraction layer with further elevated kernel and control thread application-level interfaces that directly support the high-level semantics of commonly-used in-memory data structure types (e.g., streams, arrays, linked lists, and trees) ([[http://www.ece.cmu.edu/~jhoe/distribution/2015/fpl2015.pdf |Weisz, FPL'2015]]).  
 +  * We developed the [[http://research.ece.cmu.edu/calcm/connect |CONNECT NoC Generator]] in support of CoRAM.