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fpga_architecture_for_computing [2017/10/31 00:43] – edit | fpga_architecture_for_computing [2019/03/31 14:01] – [Publications] edit | ||
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* [[http:// | * [[http:// | ||
* Joseph Melber | * Joseph Melber | ||
+ | * Marie Nguyen | ||
+ | * [[http:// | ||
* [[http:// | * [[http:// | ||
- | * [[http:// | + | * Yu Wang ([[http:// |
* Zhipeng Zhao | * Zhipeng Zhao | ||
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=====Publications===== | =====Publications===== | ||
+ | * Yu Wang, James C. Hoe, and Eriko Nurvitadhi. **Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared-Memory Platform**. | ||
+ | * Yu Wang. **Accelerating Graph Processing on a SharedMemory FPGA System**. PhD Thesis, December 2018. ([[http:// | ||
+ | * Marie Nguyen and James C. Hoe. **Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration**. Proc. International Conference on Field-programmable Logic and Applications (FPL), September 2018. ([[http:// | ||
* Marie Nguyen and James C. Hoe. **Amorphous Dynamic Partial Reconfiguration with Flexible Boundaries to Remove Fragmentation**. October 2017. ([[https:// | * Marie Nguyen and James C. Hoe. **Amorphous Dynamic Partial Reconfiguration with Flexible Boundaries to Remove Fragmentation**. October 2017. ([[https:// | ||
* Zhipeng Zhao and James C. Hoe. **Using Vivado-HLS for Structural Design: a NoC Case Study**. Unpublished Tech Report, February 2017. ([[https:// | * Zhipeng Zhao and James C. Hoe. **Using Vivado-HLS for Structural Design: a NoC Case Study**. Unpublished Tech Report, February 2017. ([[https:// |