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fpga_architecture_for_computing [2019/09/30 05:41]
edit [Network Function Acceleration]
fpga_architecture_for_computing [2019/09/30 05:42] (current)
edit [CoRAM]
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 We begin our investigation my studying FPGA acceleration of Intrusion Detection System (IDS). Today’s state of the art IDS are software-based and cannot cost- or power-efficiently keep-up with increasing network speed. ​ FPGA accelerators are promising as efficient high performance hardware alternative to software IDS and retain software’s programmability. ​ We are currently working on an FPGA accelerated SNORT IDS that uses FPGA to handle the common cases at network speed (100Gbps) and only offload a very small fraction of exceptional cases to CPU.  Future work is to create a high-level domain-specific NF programming framework for use by networking experts who are not RTL experts. ​ This is joint work with [[http://​www.justinesherry.com/​ |Justine Sherry]] and [[https://​users.ece.cmu.edu/​~vsekar/​ | Vyas Sekar]]. We begin our investigation my studying FPGA acceleration of Intrusion Detection System (IDS). Today’s state of the art IDS are software-based and cannot cost- or power-efficiently keep-up with increasing network speed. ​ FPGA accelerators are promising as efficient high performance hardware alternative to software IDS and retain software’s programmability. ​ We are currently working on an FPGA accelerated SNORT IDS that uses FPGA to handle the common cases at network speed (100Gbps) and only offload a very small fraction of exceptional cases to CPU.  Future work is to create a high-level domain-specific NF programming framework for use by networking experts who are not RTL experts. ​ This is joint work with [[http://​www.justinesherry.com/​ |Justine Sherry]] and [[https://​users.ece.cmu.edu/​~vsekar/​ | Vyas Sekar]].
-====CoRAM====+====CoRAM ​(Classic)====
 Our investigation into FPGA architecture for computing began in 2009 with the question: how should data-intensive FPGA compute kernels view and interact with external memory data.  In response, we developed the original CoRAM FPGA computing abstraction. ​ The goal of the CoRAM abstraction is to present the application developer with (1) a virtualized appearance of the FPGA’s resources (i.e., reconfigurable logic, external memory interfaces, and on-chip SRAMs) to hide low-level, non-portable platform-specific details, and (2) standardized,​ easy-to-use high-level interfaces for controlling data movements between the memory interfaces and the in-fabric computation kernels. ​  ​Besides simplifying application development,​ the virtualization and standardization of the CoRAM abstraction also make possible portable and scalable application development. Our investigation into FPGA architecture for computing began in 2009 with the question: how should data-intensive FPGA compute kernels view and interact with external memory data.  In response, we developed the original CoRAM FPGA computing abstraction. ​ The goal of the CoRAM abstraction is to present the application developer with (1) a virtualized appearance of the FPGA’s resources (i.e., reconfigurable logic, external memory interfaces, and on-chip SRAMs) to hide low-level, non-portable platform-specific details, and (2) standardized,​ easy-to-use high-level interfaces for controlling data movements between the memory interfaces and the in-fabric computation kernels. ​  ​Besides simplifying application development,​ the virtualization and standardization of the CoRAM abstraction also make possible portable and scalable application development.