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digital_signal_processing_hardware [2019/09/30 09:45] – editdigital_signal_processing_hardware [2020/09/28 21:12] – edit
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   * **[[http://www.spiralgen.com | SpiralGen, Inc]]**   * **[[http://www.spiralgen.com | SpiralGen, Inc]]**
   * **Efficient Memory Accesses**   * **Efficient Memory Accesses**
 +    * Franz Franchetti, Tze Meng Low, Doru Thom Popovici, Richard M. Veras, Daniele G. Spampinato, Jeremy R. Johnson, Markus Pueschel, James C. Hoe, and J. M. F. Moura. **SPIRAL: Extreme Performance Portability**. Proceedings of the IEEE, Special Issue on From High Level Specification to High Performance Code, November 2018.  ([[https://ieeexplore.ieee.org/document/8510983 |ieee]])
     * Fazle Sadi, Joe Sweeney, Scott McMillan, Tze Meng Low, James C. Hoe, Larry Pileggi, Franz Franchetti. **PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV**. IEEE High Performance Extreme Computing Conference (HPEC), September 2018. ([[http://www.ece.cmu.edu/~jhoe/distribution/2018/hpec18.pdf |pdf]])     * Fazle Sadi, Joe Sweeney, Scott McMillan, Tze Meng Low, James C. Hoe, Larry Pileggi, Franz Franchetti. **PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV**. IEEE High Performance Extreme Computing Conference (HPEC), September 2018. ([[http://www.ece.cmu.edu/~jhoe/distribution/2018/hpec18.pdf |pdf]])
     * Berkin Akin, Franz Franchetti, James C. Hoe. **HAMLeT Architecture for Parallel Data Reorganization in Memory**. IEEE Micro Near-Data Processing Special Issue, Jan/Feb 2016 ([[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7325181 |ieee]])      * Berkin Akin, Franz Franchetti, James C. Hoe. **HAMLeT Architecture for Parallel Data Reorganization in Memory**. IEEE Micro Near-Data Processing Special Issue, Jan/Feb 2016 ([[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7325181 |ieee]]) 
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 =====Related===== =====Related=====
     * [[18-643 Reconfigurable Logic |ECE 18-643: Reconfigurable Logic - Technology, Architecture and Applications]]     * [[18-643 Reconfigurable Logic |ECE 18-643: Reconfigurable Logic - Technology, Architecture and Applications]]
-    * [[Digital Signal Processing Hardware | Digital Signal Processing Hardware]]+    * [[FPGA Architecture for Computing]]