Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision
Previous revision
digital_signal_processing_hardware [2019/03/31 10:36]
edit
digital_signal_processing_hardware [2019/09/30 05:46]
edit
Line 57: Line 57:
     * **Fast Bilateral Filtering by Adapting Block Size**. W. Yu, F. Franchetti, J. C. Hoe, Y.-J. Chang, T. Chen. Proc. International Conference on Image Processing (ICIP), September 2010. ([[http://​www.ece.cmu.edu/​~jhoe/​distribution/​2010/​icip10.pdf |pdf]])     * **Fast Bilateral Filtering by Adapting Block Size**. W. Yu, F. Franchetti, J. C. Hoe, Y.-J. Chang, T. Chen. Proc. International Conference on Image Processing (ICIP), September 2010. ([[http://​www.ece.cmu.edu/​~jhoe/​distribution/​2010/​icip10.pdf |pdf]])
     * **Real Time Stereo Vision Using Exponential Step Cost Aggregation on GPU**. W. Yu, T. Chen, J. C. Hoe. International Conference on Image Processing (ICIP), November 2009. ([[http://​www.ece.cmu.edu/​~jhoe/​distribution/​2009/​icip09.pdf |pdf]])     * **Real Time Stereo Vision Using Exponential Step Cost Aggregation on GPU**. W. Yu, T. Chen, J. C. Hoe. International Conference on Image Processing (ICIP), November 2009. ([[http://​www.ece.cmu.edu/​~jhoe/​distribution/​2009/​icip09.pdf |pdf]])
 +
 +=====Related=====
 +    * [[18-643 Reconfigurable Logic |ECE 18-643: Reconfigurable Logic - Technology, Architecture and Applications]]
 +    * [[FPGA Architecture for Computing]]
 +