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digital_signal_processing_hardware [2019/03/31 14:36] – editdigital_signal_processing_hardware [2019/09/30 09:46] – edit
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     * **Fast Bilateral Filtering by Adapting Block Size**. W. Yu, F. Franchetti, J. C. Hoe, Y.-J. Chang, T. Chen. Proc. International Conference on Image Processing (ICIP), September 2010. ([[http://www.ece.cmu.edu/~jhoe/distribution/2010/icip10.pdf |pdf]])     * **Fast Bilateral Filtering by Adapting Block Size**. W. Yu, F. Franchetti, J. C. Hoe, Y.-J. Chang, T. Chen. Proc. International Conference on Image Processing (ICIP), September 2010. ([[http://www.ece.cmu.edu/~jhoe/distribution/2010/icip10.pdf |pdf]])
     * **Real Time Stereo Vision Using Exponential Step Cost Aggregation on GPU**. W. Yu, T. Chen, J. C. Hoe. International Conference on Image Processing (ICIP), November 2009. ([[http://www.ece.cmu.edu/~jhoe/distribution/2009/icip09.pdf |pdf]])     * **Real Time Stereo Vision Using Exponential Step Cost Aggregation on GPU**. W. Yu, T. Chen, J. C. Hoe. International Conference on Image Processing (ICIP), November 2009. ([[http://www.ece.cmu.edu/~jhoe/distribution/2009/icip09.pdf |pdf]])
 +
 +=====Related=====
 +    * [[18-643 Reconfigurable Logic |ECE 18-643: Reconfigurable Logic - Technology, Architecture and Applications]]
 +    * [[FPGA Architecture for Computing]]
 +