Synopsys Design Compiler is a software package that compiles synthesizable Verilog into a netlist to target an ASIC standard cell library. In 18-447, we will use this tool to verify that your Verilog code is, indeed, synthesizable. Design Compiler takes a special synthesis script and your synthesizable Verilog hardware description and produces a netlist and estimates for timing, power consumption, and circuit area of your circuit, optimized for your input clock rate.
We have included the Design Compiler variables in the 18-447 ModelSim environment setup scripts, so by following the ModelSim setup instructions, your environment should already be configured properly.
Design Compiler uses a special script file to setup and direct compilation of your Verilog description. These scripts are hard-coded to list which Verilog file(s) to compile, your top module for synthesis, and the name of your clock signal.
For lab0, to use
/afs/ece/class/ece447/handout/lab0/lab0.dc, the module to be synthesized must be called
FSM in a file called
FSM module must have a clock input port named
clock and a reset input port named
reset. (You can find and replace these specific names in
lab0.dc when you want to reuse the script in a future lab.)
In your working directory with both your Verilog code (e.g.,
lab0.v) and the synthesis script (e.g.,
lab0.dc), run the following command on any of ECE's Linux machines:
dc_shell -f lab0.dc
You should see a startup banner for Design Compiler and it should briefly print “Initializing…”. After this, it will read your Verilog file and load the technology library (in this case, an 180nm standard cell library). Depending on what you did, you should also expect to see a number of common warnings. You should investigate them, although many such warning messages do not indicate a show-stopper problem with your Verilog. Error messages, on the other hand, are definitely bad news.
If all goes well, the compiler should churn for a little time (or lots, depending on the complexity of your circuit). Finally, it should begin mapping your Verilog description to the standard cell library and generate reports for area, power, and timing (output in
timing.rpt, respectively). The prized netlist should also be written to the current directory.
We do not suggest modifying the dc scripts beyond changing your top module and source files. Should you be motivated to modify the synthesis script, here is a quick run through. You will have to read the documentations on your own if you really want to be good at this.
The Verilog source files are read with the command:
read -format verilog ./yourfile.v
Clearly, changing the filename will change which file gets loaded into the compiler. You can give a list of .v files to be synthesized. Similarly, your Top module can be set with:
Note that your Top module should be the top logic module that you would like to synthesize. In particular, this should not be your test bench, since that will almost definitely contain external memory arrays, non-synthisizable Verilog (such as initialization or your clock module), and other things that would make the poor synthesis tool cry, if not croak.
Finally, your clock name declaration in the top module must match the clock declared in the synthesis file (without this, the synthesis tool doesn't know which signal is a clock!). (The same goes for reset.) You must change the declaration in the following bold places to match your clock and reset port names:
create_clock -period 10.0 clk
real_inputs = all_inputs() - clk – rst
set_input_delay -clock clk -max 2.0 real_inputs
set_output_delay -clock clk -max 2.0 all_outputs()
Note that you can also increase or decrease the target clock period. If you are too aggressive, the compiler will try very hard to meet your timing requirements (sometime with ridiculous results). If you leave too much slack, the compiler won't try hard at all—but it will be much faster. If Design Compiler reports timing violations in the timing report, increase the clock period until they go away.