18-100 Course Schedule, Fall 2013

  • Lecture
    • TR 01:30PM 02:50PM PH 100
  • Recitatations
    • M 11:30AM 12:20PM WEH 4709
    • M 12:30PM 01:20PM WEH 4709
    • M 01:30PM 02:20PM PH A20
    • M 02:30PM 03:20PM DH 2105
    • M 03:30PM 04:20PM DH 2105
  • Labs
    • M/T/W/Th 06:30PM 09:20PM HH A101
    • Th 03:00PM 06:00PM HH A101
    • F 01:30PM 04:20PM HH A101

Week Date L# Topic
1 8/27 L1 Introduction, discussion of engineering systems and sub-systems, basic electricity.
8/29 L2 Voltage, current, resistance, power, circuit schematic symbols, ground.
2 9/3 L3 Power dissipation, Ohm's law, Kirchoff's Voltage and Current Laws, basic circuits.
9/5 L4 Series and parallel resistances and combinations, solving circuits using equivalent resistances.
3 9/10 L5 Superposition, Thevenin and Norton Equivalents, Source Transformation.
9/12 L6 Introduction to capacitors and inductors, impedance, begin 1st order systems.
4 9/17 L7 Continue 1st order systems, RC and LR circuits, time and freq. domain.
9/19 L8 2nd order systems, LRC circuits, frequency response.
5 9/24 L9 CIT Area Talks. Review for Exam I.
9/26 L10 Introduction to Operational Amplifiers, open and closed loop gain, op-amp assumptions, inverting and non-inverting amplifier circuits.
6 10/1 Exam I
10/3 L11 Buffers, summing and difference circuits, active filters.
7 10/8 L12 Introduction to diodes (signal, zener, and LED), basic diode operation, piecewise linear model (PWL) for diodes.
10/10 L13 Diode circuits, rectifiers, AC to DC conversion.
8 10/15 L14 Introduction to the field effect transistor (FET) and its operating regions. Common drain transistor circuit, FET switches.
10/17 L15 Small signal analysis of the common drain FET circuit. Class A amplifier.
9 10/22 L16 Finish any remaining FET concepts. Introduce signals and modulation.
10/24 L17 Sampling, analog to digital conversion, quantization, base conversions, binary arithmetic.
10 10/29 L18 Finish signal processing concept. Review for Exam II.
10/31 L19 Introduction to Computer Systems, begin basic assembly language.
11 11/5 Exam II
11/7 L20 Basic assembly language (cont.).
12 11/12 L21 Logic gates, Boolean expressions, DeMorgan's theorems, begin combinational logic circuits.
11/14 L22 Combinational logic circuits (cont.), truth tables, digital circuit schematics, two-level circuit representation.
13 11/19 L23 Karnaugh maps, adders, multiplexers, de-multiplexers.
11/21 L24 Feedback in logic circuits, SR flip-flops, D flip-flops, master-slave edge-triggered flip-flops, sequential logic, state diagrams, state transition tables, begin finite state machine design.
14 11/26 L25 Continue finite state machine design, design of counters, output mapping, sequential logic circuits with external inputs.
11/28 bonus Thanksgiving (no class)
15 12/3 L26 CIT Area Talks. Review for Exam III.
12/5 Exam III
TBD Final Exam