Computer Architecture Lab (CALCM)
Center for Silicon System Implementation (CSSI)
Department of Electrical & Computer Engineering
Carnegie Mellon University
5000 Forbes Ave.
Hamerschlag Hall, A-313
Pittsburgh, PA 15213
I am the lead student for the
Connected RAMs (CORAMs) project, an effort to rethink how FPGA
memory systems should be architected for computing. I have also led the
an effort to accelerate full-system, multiprocessor simulations using novel
FPGA approaches. This work is affiliated with the RAMP project.
My work in these areas has been generously funded in part by NSF, IBM, Intel, Sun Microsystems, Xilinx, and through a Microsoft Research Fellowship.
CoRAM: An In-Fabric Memory Abstraction for FPGA-based Computing
Eric S. Chung, James C. Hoe, and Ken Mai.
Nineteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2011.
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPUs?
Eric S. Chung, Peter A. Milder, James C. Hoe, and Ken Mai.
International Symposium on Microarchitecture (MICRO-43), Atlanta, GA, 2010.
High-Level Design and Validation of the BlueSPARC Multithreaded Processor
Eric S. Chung and James C. Hoe.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.29, no.10, pp.1459-1470, Oct. 2010.
Implementing a High-performance Multithreaded Microprocessor: A Case Study in High-level Design and Validation
Eric S. Chung and James C. Hoe.
Formal Methods and Models for Codesign (MEMOCODE), Boston, MA, 2009.
ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs
Eric S. Chung, Michael K. Papamichael, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai.
ACM Transactions on Reconfigurable Technology and Systems, 2009.
A Complexity-Effective Architecture for Accelerating Full-System Multiprocessor Simulations Using FPGAs
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai. International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2008.
Virtualized Full-System Emulation of Multiprocessors using FPGAs
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai. 2nd Workshop on Architectural Research Prototyping in conjunction with the 34th International Symposium on Computer Architecture, San Diego, June 2007.
Co-Simulation for Component-wise FPGA Emulator Development
Eric S. Chung, James C. Hoe, and Babak Falsafi. Workshop on Architecture Research using FPGA Platforms, 11th International Symposium on High-Performance Computer Architecture, Austin, TX, February 12, 2006.
Open Source Protoflex Simulator RAMP summer retreat at UT Austin, Austin, TX, 6/09.
Usability Challenges for RAMP2 RAMP spring retreat at UCB, Berkeley, CA, 1/09.
ProtoFlex Status Update and Design Experiences RAMP spring retreat at UCB, Berkeley, CA, 1/08.
Accelerating Architectural-Level Full-System Simulations Using FPGAs Guest speaker at Microsoft Research, Redmond, CA, 10/07.
Architectural Emulation on FPGAs Made Easy with Bluespec 1st Bluespec Workshop at MIT, Boston, MA, 8/07.
Protoflex: An FPGA-Accelerated Hybrid Functional Simulator RAMP winter retreat at UCB, Berkeley, CA, 1/07.
Combining Simulators and FPGAs: "An Out-of-Body Experience" RAMP summer retreat at MIT, Boston, MA, 6/06.
RAMP Simulator Tutorial: Protoflex, FAST, HAsim, and RAMP-Gold Held in conjunction with ISPASS-2010, March 28, 2010.
SimFlex and ProtoFlex
Eric Chung, Mike Ferdman, and Michael K. Papamichael. Held in conjunction with MICRO-42, December 12, 2009.
ProtoFlex: An Architectural Exploration Vehicle using FPGA-Accelerated, Full-System Multiprocessor Simulation
Eric S. Chung, Michael K. Papamichael. Held in conjunction with IISWC-2009, October 4, 2008.
ProtoFlex Tutorial: Full-System MP Simulations Using FPGAs
Eric S. Chung, Michael K. Papamichael. Held in conjunction with ASPLOS-13, March 2, 2008.
RAMP tutorial: ProtoFlex
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, and Ken Mai. Held in conjunction with ISCA-34, San Diego, CA, June 10, 2007.
TRUSS: Reliable, Scalable Server Architecture Brian T. Gold, Jared C. Smolens, Jangwoo Kim, Eric S. Chung, Vasileios Liaskovitis, Eriko Nurvitadhi, Babak Falsafi, James C. Hoe, and Andreas G. Nowatzyk. IEEE Micro, Special Issue on Reliability-Aware Microarchitectures, November-December 2005.
Opportunity of Hardware-based Optimistic Concurrency in OLTP
Jangwoo Kim, Eriko Nurvitadhi, Eric S. Chung.
Selected Project Reports from Advanced OS & Distributed Systems, Spring 2005. Technical report CMU-CS-05-138.
Design Patterns for Ubiquitous Computing
Eric S. Chung, Jason I. Hong, James Lin, Madhu K. Prabaker, James A. Landay, and Alan L. Liu.
Proceedings of Designing Interactive Systems 2004. Cambridge, Massachusetts. August, 2004.
Design and Comparison of 64-bit Re-configurable Adders
Eric S. Chung, Advanced Digital Integrated Circuits course project supervised by Borijove Nikolic. Berkeley, CA. July 2004.