From Finance to Flip Flops: Using the Mathematics of Money and Risk to Model the Statistics of Nanoscale Circuits
Group Researchers: Sonia Singhal
Collaborators: Amith Singhee, IBM; Benton H. Calhoun, U. Virginia; Xin Li, CMU
Moore's law device scaling dramatically increases the statistical variability with which tomorrow’s chips must contend. Devices with atomic dimensions don't have deterministic parameters: every behavior we want to model is a messy smear of probability. How should we attack such problems? Is slow, expensive Monte Carlo analysis our only option? Is the silicon community unique in facing such problems? As it turns out, problems in computational finance and risk analysis share many of the characteristics that challenge us in statistical circuit analysis: high dimensionality, profound nonlinearity, stringent accuracy requirements, and expensive analysis (i.e., circuit simulation). This project is adapting computational ideas from Wall Street for use in the silicon world. The same methods used to price complex securities can be adapted to compute silicon yields, giving speedups of 2x - 50x. Methods used to analyze the statistics of rare events (like the size of the biggest wave in a hurricane like Katrina) can be used to analyze failures in SRAM, giving speedups of 20,000x.
- Amith Singhee and Rob A. Rutenbar, “From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis,” Proc.
IEEE 8th International Symposium on Quality Electronic Design (ISQED),
March 2007. pdf
- Amith Singhee and Rob A. Rutenbar, “Statistical Blockade: A Novel Method for Very Fast Money Carlo Simulation of Rare Circuit Events, and its Application ," Proceedings
of the 10th Conference on Design, Automation and Test in Europe (DATE
07), April 2007. Winner, DATE2007 Best Paper. pdf
- Amith Singhee and Rob A. Rutenbar, “Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting,” Proc.
ACM/IEEE Design Automation Conference, June 2007. pdf
- J. Wang, A. Singhee, R.A. Rutenbar, B. H. Calhoun, “Modeling the Minimum Standby Supply Voltage of a Full SRAM Array,” Proc.
European Solid State Circuits Conference (ESSCIRC), October 2007. pdf
- R.A. Rutenbar, "From Wall Street to Silicon Valley: Using the Mathematics of Money & Risk for Fast Statistical IC Design ," Invited Keynote given at 5th Int’l
System-on-Chip (SoC) Conference, Nov. 2007. pdf
- A. Singhee, J. Wang, B. H. Calhoun, R. A. Rutenbar, “Recursive Statistical Blockade,” Proc.
2008 International Conference on VLSI, January 2008. Winner, Best Student
Paper Award. pdf
- A. Singhee, S. Singhal, R. A. Rutenbar, “Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing,” Proc.
Design Automation and Test in Europe Conference (DATE), March 2008. pdf
- Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi, Rob
A. Rutenbar and Kenneth L. Shepard, “Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS,” Proceedings
of the IEEE, Vol. 96, No. 2, pages 343-365, February 2008. pdf
- Rob A. Rutenbar, "From FInance to Flip Flops: Using the Mathematics of Money and Risk to Understand the Statistics of Nanoscale Circuits" , invited talk given at Cadence Design Systems, Oct 2008. pdf
- Amith Singhee, Sonia Singhal, Rob A. Rutenbar, "Practical, Fast Monte Carlo Static Timing Analysis: Why and How," Proc. ACM/IEEE International Conference on CAD, Nov 2008. pdf
- Rob A. Rutenbar, "From FInance to Flip Flops: Using the Mathematics of Money and Risk to Understand the Statistics of Nanoscale Circuits" , invited talk given at CANDE'08 Workshop, Nov 2008. pdf