Encrypted Computing

Overview

The goal of this research is to develop novel computing systems that enable encrypted computation for IoT netwoks. Consider a network of sensors collecting private data and utilizing a more robust edge device to perform functions such as DNN inference. Recent advances in theoretical cryptography have shown the feasibility of Fully Homomorphic Encryption (FHE) which would allow the edge device to perform privacy preserving computation directly on encrypted data. Unfortunately, a single FHE ciphertext includes thousands of values and encrypted operations are orders-of-magnitude more expensive than their standard counterparts. My work addresses these exciting challenges at both a software and hardware level by exploring clever algorithms and efficient architectures that operate within the constrained context of IoT devices.

Client-Optimized Algorithms and Acceleration for Encrypted Compute Offloading

McKenzie van der Hagen and Brandon Lucia
ASPLOS '23 | Lausanne, Switzerland | February 2022

Paper | Presentation

A 10.33µJ/encryption Homomorphic Encryption Engine in 28nm CMOS with 4096-degree 109-bit Polynomials for Resource-Constrained IoT Clients

Siddharth Das, McKenzie van der Hagen, Swarali Patil, Cagri Erbagci, Ken Mai, and Brandon Lucia
ESSCIRC '23 | Lisbon, Portugal | September 2023

Paper

Unary Positional Computing

Unary Positional Computing

McKenzie van der Hagen and Marc Riedel
IEEE Global Conference on Signal and Information Processing | November 2017

This paper introduces a novel representation that is a hybrid of unary and positional systems. It builds upon unary computation, a recent evolution in the field of stochastic computing. In contrast to the stochastic approach, the unary approach is completely accurate, with no random fluctuations. It requires less area and has much lower latency. However, compared to a conventional binary approach, the latency is still unacceptably high for many applications. The unary positional system proposed in this paper reduces the latency exponentially, with only a modest increase in the hardware complexity. Constructs for arithmetic operations such as addition and multiplication are presented and their performance is evaluated.

Paper | Poster