Thursday, November 21, 2013

8:00AM ~ 8:15AM: Opening Remarks

8:15AM ~ 10:00AM: Session I: Emerging Design Methodologies
Chair: Brian Chen, Agilent Technologies

Using Sub-Harmonic Injection Locking to Enable Phase-Based Logical Computation
Jaijeet Roychowdhury, University of California, Berkley

Components and Modeling Implications for Short-Reach Optical Interconnects
Frankie Liu, Oracle

Improving Accessibility in Mixed-Signal Design
John Maddux, Intel

10:00AM ~ 10:15AM: Break

10:15AM ~ 12:00PM: Session II: Design Challenges at Advanced Nodes
Chair: Omeed Momeni, University of California, Davis

Custom and Analog Design Challenges with Advanced Node Process
Gilles Lamant, Cadence Design Systems

FinFET Variability and Its Impact on Digital and Analog Circuits
Victor Moroz, Synopsys

AMS Verification for High Reliability and Safety Critical Applications
Martin Vlach, Mentor Graphics

12:00PM ~ 1:00PM: Lunch

1:00PM ~ 2:45PM: Session III: Synthesis and Testing
 Chair: Chirayu Amin, Intel

Test Data Analytics - Exploring Hidden Patterns in Production Test Data for Silicon Characterization and Test Prediction
Tim Cheng, University of California, Santa Barbara

Constraints - The Key to Analog Design Automation
Helmut Graeb, Technische Universitaet Muenchen

Paving The Way for New Sizing Approaches of Analog and RF Integrated Circuits
Francisco. V. Fernandez, CSIC and Univ. of Sevilla

2:45PM ~ 3:00PM: Break

3:00PM ~ 4:00PM: Poster Session

Poster List

Time-domain Performance Bound Analysis for Analog and Interconnect Circuits Considering Process Variations
Tan Yu, University of California, Riverside, USA
Zao Liu, University of California, Riverside, USA
Sheldon Tan, University of California, Riverside, USA

Graph Sparsification Approach to Scalable Harmonic Balance Analysis of RF Circuits
Lengfei Han, Michigan Technological University, USA
Xueqian Zhao, Michigan Technological University, USA
Zhuo Feng, Michigan Technological University, USA

Analog Placement Considering Monotonic Current/Signal Flows
Po-Hsun Wu, National Cheng Kung University, Taiwan
Tsung-Yi Ho, National Cheng Kung University, Taiwan
Ching-Feng Yeh, National Chung Cheng University, Taiwan
Mark Po-Hung Lin, National Chung Cheng University, Taiwan
Tung-Chieh Chen, Synopsys, TaiWan

Frequency- and Time-Independent Minimal-Order Circuit Model with Frequency- and Time-Independent Minimal-Order Circuit Model with Electromagnetic Accuracy and Its Application to Fast Circuit Simulation
Qing He, Purdue University, USA
Duo Chen, Purdue University, USA
Dan Jiao, Purdue University, USA

A Reduced Set of Traces for the Verification of Hybrid Systems with Ranges of Rates
Andrew Fisher, University of Utah, USA
Chris Myers, University of Utah, USA
Peng Li, Texas A&M University, USA

ADAMS: Asymmetric Differential MRAM Cell Structure
Yaojun Zhang, University of Pittsburgh, USA
Yu Wang, University of Pittsburgh, USA
Hai Li, University of Pittsburgh, USA
Yiran Chen, University of Pittsburgh, USA

ABCD: Accurate and Scalable Modelling of Linear and Non-Linear Analog/Mixed-Signal Systems Using Purely Boolean Approximations
Aadithya Karthik, University of California, Berkeley, USA
Sayak Ray, University of California, Berkeley, USA
Pierluigi Nuzzo, University of California, Berkeley, USA
Alan Mishchenko, University of California, Berkeley, USA
Robert Brayton, University of California, Berkeley, USA
Jaijeet Roychowdhury, University of California, Berkeley, USA

Checking Start-up Failures in Coupled Ring Oscillators in Presence of Variability Using Predictive Global Optimization
Taehwan Kim, Seoul National University, South Korea
Do-Gyoon Song, Seoul National University, South Korea
Sangho Youn, Seoul National University, South Korea
Jaejin Park, Samsung Electronics, South Korea
Hojin Park, Samsung Electronics, South Korea
Jaeha Kim, Seoul National University, South Korea

A Case Study for Topology Synthesis using Symbolic Comparison and Nodal Feature Clustering
Cristian Ferent, Stony Brook University, USA
Alex Doboli, Stony Brook University, USA

Verifying Global Convergence of a Digital Phase-Locked Loop with Z3
Yan Peng, University of British Columbia, Canada
Mark Greenstreet, University of British Columbia, Canada

Modeling and Digital Correction of Summing-Node Leakage in SAR ADCs
Brian Elies, University of Texas at Dallas, USA
Yun Chiu, University of Texas at Dallas, USA

SPICE-Level Non-Monte Carlo Uncertainty Quantification for Integrated Circuits
Zheng Zhang, Massachusetts Institute of Technology, USA
Ibrahim Elfadel, Masdar Institute of Science and Technology, United Arab Emirates
Luca Daniel, , Massachusetts Institute of Technology, USA

Random Input Sampling for Complex Stochastic Models using Markov Chain Monte Carlo
Ahmet Mahmutoglu, Koc University, Turkey
Alper Erdogan, Koc University, Turkey
Alper Demir, Koc University, Turkey

Concurrent Data Sorting for Circuit Sample Classification Based on GPGPU
Santiago Rodriguez-Chavez, INAOE, Mexico
Esteban Tlelo-Cuautle, INAOE, Mexico

Indirect Performance Sensing for On-Chip Analog Self-Healing via Bayesian Model Fusion
Shupeng Sun, Carnegie Mellon University, USA
Fa Wang,  Carnegie Mellon University, USA
Soner Yaldiz,  Carnegie Mellon University, USA
Xin Li,  Carnegie Mellon University, USA
Larry Pileggi, Carnegie Mellon University, USA
Arun Natarajan, IBM T. J. Watson Research Center, USA
Mark Ferriss, IBM T. J. Watson Research Center, USA
Jean-Olivier Plouchart, IBM T. J. Watson Research Center, USA
Bodhisatwa Sadhu, IBM T. J. Watson Research Center, USA
Ben Parker, IBM T. J. Watson Research Center, USA
Alberto Valdes-Garcia, IBM T. J. Watson Research Center, USA
Mihai Sanduleanu, IBM T. J. Watson Research Center, USA
Jose Tierno, IBM T. J. Watson Research Center, USA
Daniel Friedman, IBM T. J. Watson Research Center, USA