Y4 Publications

In the News:

In July 1997 issue of Semiconductor International, the editors of the magazine published a report on Y4 in the Industry News section titled "Assessing Cost vs. Yield Trade-Offs in the Fab," pp. 28 and 30. This article is scanned and reproduced here. This page may take a while to load.

The relevant publications are:

.P.K. Nag, W. Maly and H. Jacobs, “Advanced Forecasting of Cost and Yield,” Semiconductor International, pp. 163 - 170, July 1998.

Abstract:

This article describes a prototype of a discrete event simulator - Y4 (Yield Forecaster) - capable of simulating defect related yield loss as a function of time, for a multi-product IC manufacturing line. The methodology of estimating yield and cost is based on mimicking the operation and characteristics of a manufacturing line in the time domain. The effect of particles introduced during wafer processing as well as changes in their densities due to process improvements are taken into account. A spectrum of results are presented for a manufacturing scenario to demonstrate the usefulness of the simulator in formulating IC manufacturing strategies.

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P. K. Nag, W. Maly and H. Jacobs, "Simulation of Yield/Cost Learning Curves with Y4," in Transactions on Semiconductor Manufacturing, vol. 10, no.2, pp. 256-266, May 1997.

Abstract:

This paper describes a prototype of a discrete event simulator - Y4 (Yield Forecaster) - capable of simulating defect related yield loss as a function of time, for a multi-product IC manufacturing line. The methodology of estimating yield and cost is based on mimicking the operation and characteristics of a manufacturing line in the time domain. The paper presents a set of models that take into account the effect of particles introduced during wafer processing as well as changes in their densities due to process improvements. These models also illustrate a possible way of accounting for the primary attributes of fabrication, product and failure analysis which affect yield learning. A spectrum of results are presented for a manufacturing scenario to demonstrate the usefulness of the simulator in formulating IC manufacturing strategies.

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Pranab K. Nag, "Yield Forecasting," Ph.D. Dissertation, Dept. of Electrical and Computer Engineering, Carnegie Mellon University, April, 1996.

Abstract:

Success of modern semiconductor manufacturing has been achieved through a number of key innovations in the areas of IC design, manufacturing, testing and failure analysis. Research and development in each of these areas have grown to such a level of complexity - reflecting the complexity of today's industry - that the inter-dependence among these areas has largely been side-tracked. But the performance of a semiconductor industry is not only dependent on the advancements in these individual areas but also on their interactions.

One of the significant detractors of cost in a modern manufacturing line is yield loss due to contamination and the time required to ramp-up the yield to profitable levels. Yield loss and its rate of change with time in a manufacturing line is determined by the various attributes of fabrication, product, testing and failure analysis and their interactions which determine yield learning rate. This research attempts to gain an understanding of the nature of this inter-relationship by addressing the problem of predicting yield as a function of time for a multi-product manufacturing line.

In this thesis, first the process of contamination related yield learning as it happens in a manufacturing line is presented. Then a methodology to predict yield learning curves for a multi-product manufacturing line is proposed. A suite of models has been developed which capture the primary factors determining yield learning rate. The methodology and models have been implemented in a discrete event simulator - Y4 (Yield Forecaster). Through a series of simulation experiments, estimates of performance parameters like cycle time, yield, test escapes, and learning rate are presented to illustrate some of models individually. Then another series of experiments are presented to illustrate the applicability of Y4 in performing cost-revenue trade-off studies for a variety of situations.

Through these experiments, it is concluded that more attention must be devoted to characterizing those attributes of product and failure analysis that determine the ease of diagnosis. But more importantly, the inter-relationship between manufacturing entities should be characterized well in order to be able to and determine cost benefits of making improvements in the design objectives.

Get the thesis

P. K. Nag and W. Maly, "Yield Learning Simulation," Proc. of TECHCON '93, pp. 280-282, Oct. 1993.

Abstract:

In this paper, a method to predict defect-related yield as a function of time for a semiconductor manufacturing facility is presented. The effect of contamination-related defects on yield, and the reduction in defect levels, resulting from failure analysis, have been considered. The developed yield learning model is incorporated in a prototype simulator - Y4 - which mimics both the fabrication and the failure analysis processes. Results are presented for a spectrum of examples to illustrate the use of the simulator in formulating IC manufacturing strategies.

Get the paper

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	In the News: In July 1997 issue of Semiconductor International, the editors of the magazine published a report on Y4 in the Industry News section titled "Assessing Cost vs. Yield Trade-Offs in the Fab," pp. 28 and 30. This article is scanned and reproduced here. This page may take a while to load. The relevant publications are: .P.K. Nag, W. Maly and H. Jacobs, “Advanced Forecasting of Cost and Yield,” Semiconductor International, pp. 163 - 170, July 1998. Abstract: This article describes a prototype of a discrete event simulator - Y4 (Yield Forecaster) - capable of simulating defect related yield loss as a function of time, for a multi-product IC manufacturing line. The methodology of estimating yield and cost is based on mimicking the operation and characteristics of a manufacturing line in the time domain. The effect of particles introduced during wafer processing as well as changes in their densities due to process improvements are taken into account. A spectrum of results are presented for a manufacturing scenario to demonstrate the usefulness of the simulator in formulating IC manufacturing strategies. Get the paper P. K. Nag, W. Maly and H. Jacobs, "Simulation of Yield/Cost Learning Curves with Y4," in Transactions on Semiconductor Manufacturing, vol. 10, no.2, pp. 256-266, May 1997. Abstract: This paper describes a prototype of a discrete event simulator - Y4 (Yield Forecaster) - capable of simulating defect related yield loss as a function of time, for a multi-product IC manufacturing line. The methodology of estimating yield and cost is based on mimicking the operation and characteristics of a manufacturing line in the time domain. The paper presents a set of models that take into account the effect of particles introduced during wafer processing as well as changes in their densities due to process improvements. These models also illustrate a possible way of accounting for the primary attributes of fabrication, product and failure analysis which affect yield learning. A spectrum of results are presented for a manufacturing scenario to demonstrate the usefulness of the simulator in formulating IC manufacturing strategies. Get the paper Pranab K. Nag, "Yield Forecasting," Ph.D. Dissertation, Dept. of Electrical and Computer Engineering, Carnegie Mellon University, April, 1996. Abstract: Success of modern semiconductor manufacturing has been achieved through a number of key innovations in the areas of IC design, manufacturing, testing and failure analysis. Research and development in each of these areas have grown to such a level of complexity - reflecting the complexity of today's industry - that the inter-dependence among these areas has largely been side-tracked. But the performance of a semiconductor industry is not only dependent on the advancements in these individual areas but also on their interactions. One of the significant detractors of cost in a modern manufacturing line is yield loss due to contamination and the time required to ramp-up the yield to profitable levels. Yield loss and its rate of change with time in a manufacturing line is determined by the various attributes of fabrication, product, testing and failure analysis and their interactions which determine yield learning rate. This research attempts to gain an understanding of the nature of this inter-relationship by addressing the problem of predicting yield as a function of time for a multi-product manufacturing line. In this thesis, first the process of contamination related yield learning as it happens in a manufacturing line is presented. Then a methodology to predict yield learning curves for a multi-product manufacturing line is proposed. A suite of models has been developed which capture the primary factors determining yield learning rate. The methodology and models have been implemented in a discrete event simulator - Y4 (Yield Forecaster). Through a series of simulation experiments, estimates of performance parameters like cycle time, yield, test escapes, and learning rate are presented to illustrate some of models individually. Then another series of experiments are presented to illustrate the applicability of Y4 in performing cost-revenue trade-off studies for a variety of situations. Through these experiments, it is concluded that more attention must be devoted to characterizing those attributes of product and failure analysis that determine the ease of diagnosis. But more importantly, the inter-relationship between manufacturing entities should be characterized well in order to be able to and determine cost benefits of making improvements in the design objectives. Get the thesis P. K. Nag and W. Maly, "Yield Learning Simulation," Proc. of TECHCON '93, pp. 280-282, Oct. 1993. Abstract: In this paper, a method to predict defect-related yield as a function of time for a semiconductor manufacturing facility is presented. The effect of contamination-related defects on yield, and the reduction in defect levels, resulting from failure analysis, have been considered. The developed yield learning model is incorporated in a prototype simulator - Y4 - which mimics both the fabrication and the failure analysis processes. Results are presented for a spectrum of examples to illustrate the use of the simulator in formulating IC manufacturing strategies. Get the paper
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