In this page we demonstrate a relatively simple scenario which can be simulated using Y4. Y4 was setup to mimic a 0.5 micron 3-metal CMOS process for a 1.4 sq. cm. micro-processor like IC. First. it was assumed that only in-line particle monitors are deployed for yield improvement. the resulting lot-by-lot yield as a function of time is shown in the next figure. Details of this particular simulation is available in the paper.     Figure 1. Particle monitor initiated yield learning. Next, the particle monitors were de-activated and only off-line failure analysis was simulated resulting in the yield learning curve of the next figure.   Figure 2. Failure analysis initiated yield learning. Then, in the next simulation both the yield improvement methods were concurrenly applied resulting in the next figure. Note the dramatic improvement in yield learning rate (all three scenarios are depicted for comparison).   Figure 3. Comparison of the three yield learning scenarios. Cost calculations were also performed and they are summarized in the next table. Obviously the case with both yield improvement methods is advantageous. The point is that the advantage can be quantified easily using Y4. Table 1: Cost Comparision    Particle Monitors only  Failure Analysis Only  Both Together  Total number of good die (in millions)  2.14 4.45  5.65  Cost of good die (in $)  167  78  65  Total product cost (in million $)  359  342  371  % cost from failure analysis  0  3.48  3.24  Time to reach 2 million good die (in weeks)  36.5  25.5  20  Number of good die in 20 weeks (in 1000's)  654  1094  2000   For more information on the results please look into the publications or send and e-mail to me.
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