Stack Computers: the new wave © Copyright 1989, Philip Koopman, All Rights Reserved.
Historically, computer designs that promise a great deal of support for high level language processing have offered the most hardware stack support. This support ranges from a stack pointer register to multiple hardware stack memories within the central processing unit. Two recent classes of processors have provided renewed interest in hardware stack support: RISC processors, which frequently feature a large register file arranged as a stack, and stack oriented real time control processors, which use stack instructions to reduce program size and processor complexity.
A taxonomy is an important step in understanding the nature of stack oriented computers. A good taxonomy allows making observations about global design tradeoff issues without delving into the implementation details of a particular machine. A taxonomy also helps in understanding where a proposed architecture stands with respect to existing designs. The purpose of beginning our discussion of stack machines with a taxonomy is to get a glimpse of the bigger picture before we focus in on multiple-stack, 0-operand machines in the following chapters.
In Section 2.1 we shall describe a taxonomy for stack machines based on three attributes: the number of stacks, the size of stack buffer memories, and the number of operands in the instruction format. We shall also discuss the strengths and weaknesses inherent in the design tradeoffs that result in a particular machine belonging to one of the taxonomy categories.
In Section 2.2 we shall categorize most published stack machine designs according to the taxonomy, then in Section 2.3 we shall looking for similarities and differences within the taxonomy groupings. The similarities within each grouping and differences between groupings show that the taxonomy helps us to think about the tradeoffs made in designing stack machines.
Phil Koopman -- firstname.lastname@example.org