First Workshop on Compiler and Architectural Techniques
for Application Reliability and Security (CATARS)
In Conjunction with the International Conference on Dependable Systems and
Networks ( DSN 2008)
Date: June 26th, 2008
Place: Anchorage, Alaska, USA
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Theme, Goals and Objectives
As computer systems grow more and more complex, it becomes harder to ensure
that they operate in a reliable and secure fashion. The problem is especially
severe at the application-level, due to the diversity of software platforms and
the ever-increasing demand for adding new features in applications. Manual
addition of ad-hoc techniques to ensure application fault and attack tolerance
may be error-prone and runs the risk of missing important reliability loopholes
and security vulnerabilities. This in turn can lead to catastrophic failures
and devastating attacks. Compiler and architectural techniques can play a
crucial role in automating both detection of and recovery from errors and
attacks in applications.
The goal of this workshop is to provide a common platform for researchers in
the dependability and security communities to interact with compiler designers
and computer architects, so that effective cross pollination of ideas can occur
between these areas. Further, the workshop will stress on the importance of
designing for reliability and security in the computer architecture and
compiler communities, where traditionally the emphasis has been on performance
enhancement.
The objectives that we plan to achieve during the workshop are as follows:
- Define core dependability issues that can be effectively addressed in the
compiler and architecture communities in order to improve the resilience of
applications. For example, “How do we implement compiler transformations
that improve application resilience to transient and permanent hardware
errors?” or “How do we ensure that microprocessors provide
transparent error containment and recovery to applications?”
- Discuss how we can leverage the latest advances in computer architecture
(such as multi-core platforms, reconfigurable computing) and in compiler
technology (such as dynamic code generation, verifiable code transformations)
to improve the dependability of applications.
- Identify means for evaluating compiler and architectural techniques in
terms of their costs and the dependability benefits they provide to
applications in order to come up with a “ready reckoner” for
engineers who wish to deploy such techniques in the field.
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List of Topics
The workshop is open to all interested researchers in the dependability and
security areas as well as in the computer architecture and compiler areas. We
encourage submissions including but not limited to the following areas:
- Automated derivation and runtime enforcement of application invariants
- Compile-time techniques for finding programming errors and security
violations
- Compiler and runtime techniques to aid development of distributed,
fault-tolerant programs
- Novel application-level code and data duplication techniques (in hardware
or software)
- Static Analysis to ensure conformance to reliability and security
properties
- Automated generation of fault-tolerant and attack-tolerant programs
- Micro-architectural techniques for runtime error detection and containment
- Architectural support for diagnosing and understanding application
failures and compromises
- Memory organization schemes for enabling detection of and recovery from
errors and attacks
- Design and Implementation of reconfigurable hardware for executing
application-level checks
- Reliability and security issues exposed due to multi-core processors and
their mitigation
- Novel programming language-level constructs for building fault-tolerant
applications
- Metrics for assessing application vulnerability to errors and security
attacks
- Verifiable byte-code/intermediate language and secure runtime
infrastructures
- Software obfuscation and hardware tamper-resistance
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Submission Information
Submitted papers must be original work with no substantial overlap with
papers that have been published or that are simultaneously published to a
journal or conference with proceedings. Papers should be
atmost 6 pages in IEEE proceedings style (two-column pages, single space,
using 10 point font and 1-inch margins)including all figures and references.
We also encourage position papers and work-in-progress reports. These will be refereed
on basis of the novelty of the idea and the ability to generate discussion at the workshop.
Position-papers and work-in-progress reports must be clearly marked as such.
Submitted papers will be fully refereed by PC members. Accepted papers will be published in the
supplemental volume of DSN 2008 proceedings
(and are not archived in the IEEE digital library).
Authors of accepted papers must guarantee that their paper will be presented at the workshop.
Submission will be via web site only.
(NEW)
All papers must be submitted at this site
The above site will take you to a form with the following fields. Please adhere carefully to the following instructions when submitting your paper.
- File to send: Only PDF files will be accepted. Please use the following naming convention for your file.
CATARS_X_Y_n.pdf
- X is the first author's last name
- Y is an abbreviation of the first author's institution
- n is 0 for your first paper. Increment n for each additional paper you submit to the workshop.
- Recipient's email address: Please fill in "jhoe+DSN@ece.cmu.edu"
- Your name: Please give the first author's full name and institution.
- Your email address: Please give the email address at which you wish to receive the acknowledgement. Please allow 48 hours. If you experience any difficulties, please email: jhoe+DSN@ece.cmu.edu
If you have any questions about the submission process, please contact: Karthik Pattabiraman
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Important Dates
- Paper submission due: March 7, 2008
- Acceptance notification: April 11, 2008
- Camera-ready versions of papers: May 1, 2008
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Organizing Committee
Co-Chairs:
- Karthik Pattabiraman, University of Illinois at Urbana-Champaign, IL
(pattabir@uiuc.edu)
- Shuo Chen, Microsoft Research, Redmond, WA (shuochen@microsoft.com)
- Zbigniew Kalbarczyk, University of Illinois at Urbana-Champaign, IL
(kalbar@crhc.uiuc.edu)
Program Committee:
- Todd Austin, University of Michigan (Ann Arbor)
- Emery Berger, University of Massachusets(Amherst)
- Michael Hicks, University of Maryland (College Park)
- Subhasish Mitra, Stanford University
- Shubu Mukherjee, Intel Corporation
- Onur Mutlu, Microsoft Research
- Priya Narasimhan, Carnegie Mellon University
- Sanjay Patel, University of Illinois (Urbana-Champaign)
- Josyula Rao, IBM Research (T J Watson)
- Zhendong Su, University of California (Davis)
- Timothy Tsai, Hitachi Corporation
- Dongyan Xu, Purdue University (West Lafayette)
- Jun Xu, Google Inc
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