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| ====== James C. Hoe's Home Page ====== | ====== James C. Hoe's Home Page ====== | ||
| - | I am a Professor of [[http://www.ece.cmu.edu |Electrical and Computer Engineering]] at [[http://www.cmu.edu |Carnegie Mellon University]]. ([[https://www.ece.cmu.edu/directory/bios/hoe-james.html |My official webpage]].) My [[Research|research interests]] include computer architecture, reconfigurable computing and high-level hardware description and synthesis. I received my Ph.D. in EECS from MIT in 2000 (S.M., 1994). I received my B.S. in EECS from UC Berkeley in 1992. I am an IEEE Fellow. | + | I am a Professor of [[http://www.ece.cmu.edu |Electrical and Computer Engineering]] at [[http://www.cmu.edu |Carnegie Mellon University]]. ([[https://www.ece.cmu.edu/directory/bios/hoe-james.html |My official webpage]].) My [[Research|research interests]] include computer architecture, reconfigurable computing and high-level hardware description and synthesis. I received my Ph.D. in EECS from MIT in 2000 (S.M., 1994). I received my B.S. in EECS from UC Berkeley in 1992. |
| + | I am currently serving as the Associate Editor-in-Chief of [[https://www.computer.org/csdl/journals/tc |IEEE Transactions on Computers (IEEE-TC)]]. | ||
| + | I am an IEEE Fellow (2013). | ||
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| * [[Advice Column |Recommendations for ECE undergrads]] | * [[Advice Column |Recommendations for ECE undergrads]] | ||
| - | * [[https://users.ece.cmu.edu/~jhoe/distribution/2017/18643-L07-essential.pdf |Very short lesson on RTL Verilog]] | ||
| - | * [[https://research.ece.cmu.edu/~coram/doku.php?id=connect-hls |Can you use Vivado-HLS where you should be using Verilog?]] | ||
| * [[FPGA Architecture for Computing]] | * [[FPGA Architecture for Computing]] | ||
| * [[https://research.ece.cmu.edu/~calcm |Computer Architecture Seminars (CALCM)]] | * [[https://research.ece.cmu.edu/~calcm |Computer Architecture Seminars (CALCM)]] | ||
| + | * [[https://users.ece.cmu.edu/~jhoe/distribution/2017/18643-L07-essential.pdf | Very short lesson on RTL Verilog]] | ||
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