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| bhsc14 [2021/06/17 16:18] – [Lecture Topics] edit | bhsc14 [2021/11/22 03:31] (current) – edit |
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| (Note: Most of the materials has since made it into [[18-643_reconfigurable_logic |18-643]]) | (Note: Most of the materials has since made it into [[18-643_reconfigurable_logic |18-643]]) |
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| * Introduction ([[http://www.ece.cmu.edu/~jhoe/distribution/bhsc14/BH0-Intro.pdf |slides]]) | * Introduction ([[https://users.ece.cmu.edu/~jhoe/distribution/bhsc14/BH0-Intro.pdf |slides]]) |
| * Essential Hardware Design Concepts ([[http://www.ece.cmu.edu/~jhoe/distribution/bhsc14/BH1-Basic.pdf |slides]] — [[18-100_course_schedule_fall_2013|CMU 18-100 L21~L25]]) | * Essential Hardware Design Concepts ([[https://users.ece.cmu.edu/~jhoe/distribution/bhsc14/BH1-Basic.pdf |slides]] — [[18-100_course_schedule_fall_2013|CMU 18-100 L21~L25]]) |
| * Operation-Centric Hardware Design and Synthesis (Bluespec) ([[http://www.ece.cmu.edu/~jhoe/distribution/bhsc14/BH2-TRSpec.pdf |slides]] — [[operation_centric_hardware_abstraction|project website]] — [[http://wiki.bluespec.com/|Bluespec]]) | * Operation-Centric Hardware Design and Synthesis (Bluespec) ([[https://users.ece.cmu.edu/~jhoe/distribution/bhsc14/BH2-TRSpec.pdf |slides]] — [[operation_centric_hardware_abstraction|project website]] — [[http://wiki.bluespec.com/|Bluespec]]) |
| * C-to-Hardware Design and Synthesis ([[http://www.ece.cmu.edu/~jhoe/distribution/bhsc14/BH3-CtoH.pdf |slides]] — [[http://ieeexplore.ieee.org/xpl/tocresult.jsp?reload=true&isnumber=5209950|D&T Special Issue]]) | * C-to-Hardware Design and Synthesis ([[https://users.ece.cmu.edu/~jhoe/distribution/bhsc14/BH3-CtoH.pdf |slides]] — [[http://ieeexplore.ieee.org/xpl/tocresult.jsp?reload=true&isnumber=5209950|D&T Special Issue]]) |
| * Domain-Specialized High-level Synthesis (Spiral) ([[http://www.ece.cmu.edu/~jhoe/distribution/bhsc14/BH4-Spiral.pdf |slides]] — [[digital_signal_processing_hardware|project website]] — [[http://www.spiral.net/hardware/dftgen.html|DFTgen]]) | * Domain-Specialized High-level Synthesis (Spiral) ([[https://users.ece.cmu.edu/~jhoe/distribution/bhsc14/BH4-Spiral.pdf |slides]] — [[digital_signal_processing_hardware|project website]] — [[http://www.spiral.net/hardware/dftgen.html|DFTgen]]) |
| * “Smart” IP-Based Design (Pandora) ([[http://www.ece.cmu.edu/~jhoe/distribution/bhsc14/BH5-SmartIP.pdf |slides]] — [[https://research.ece.cmu.edu/calcm/new_connect/connect/ |CONNECT NoC Generator]]) | * “Smart” IP-Based Design (Pandora) ([[https://users.ece.cmu.edu/~jhoe/distribution/bhsc14/BH5-SmartIP.pdf |slides]] — [[https://research.ece.cmu.edu/calcm/new_connect/connect/ |CONNECT NoC Generator]]) |
| * Infrastructure and Virtualization (CoRAM) ([[http://www.ece.cmu.edu/~jhoe/distribution/bhsc14/BH6-CoRAM.pdf |slides]] — [[fpga_architecture_for_computing|project website]] — [[http://research.ece.cmu.edu/~coram/doku.php?id=corflow_beta|try it out]]) | * Infrastructure and Virtualization (CoRAM) ([[https://users.ece.cmu.edu/~jhoe/distribution/bhsc14/BH6-CoRAM.pdf |slides]] — [[fpga_architecture_for_computing|project website]] — [[http://research.ece.cmu.edu/~coram/doku.php?id=corflow_beta|try it out]]) |
| * Performance, Power and Energy of Hardware Acceleration ([[http://www.ece.cmu.edu/~jhoe/distribution/bhsc14/BH7-Accel.pdf |slides]] — [[http://www.ece.cmu.edu/~jhoe/distribution/2010/micro10.pdf|background reading]]) | * Performance, Power and Energy of Hardware Acceleration ([[https://users.ece.cmu.edu/~jhoe/distribution/bhsc14/BH7-Accel.pdf |slides]] — [[https://users.ece.cmu.edu/~jhoe/distribution/2010/micro10.pdf|background reading]]) |
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| For more than 15 years, Dr. Hoe has actively researched languages and tools to support hardware design and synthesis from a high-level of abstraction. Dr. Hoe’s PhD research investigated a novel “operation-centric” high-level hardware design abstraction and its synthesis. As a member of the SPIRAL project team at Carnegie Mellon since 2003, Dr. Hoe has led the project branch in creating an automatic hardware design compiler for linear transforms. Dr. Hoe's other significant research efforts occupy the intersection of reconfigurable logic and computer architecture. Between 2005 and 2010, Dr. Hoe researched FPGA-accelerated simulation technology to deliver the necessary simulation performance to enable full-scale software research on top of simulated experimental architectures. Dr. Hoe's current major research focus is on devising a new FPGA architecture for power efficient, high-performance computing. | For more than 15 years, Dr. Hoe has actively researched languages and tools to support hardware design and synthesis from a high-level of abstraction. Dr. Hoe’s PhD research investigated a novel “operation-centric” high-level hardware design abstraction and its synthesis. As a member of the SPIRAL project team at Carnegie Mellon since 2003, Dr. Hoe has led the project branch in creating an automatic hardware design compiler for linear transforms. Dr. Hoe's other significant research efforts occupy the intersection of reconfigurable logic and computer architecture. Between 2005 and 2010, Dr. Hoe researched FPGA-accelerated simulation technology to deliver the necessary simulation performance to enable full-scale software research on top of simulated experimental architectures. Dr. Hoe's current major research focus is on devising a new FPGA architecture for power efficient, high-performance computing. |
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| For more information, please visit http://www.ece.cmu.edu/~jhoe. | For more information, please visit https://users.ece.cmu.edu/~jhoe. |
