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| 18-643_course_schedule_fall_2017 [2017/10/27 12:45] – [References] edit | 18-643_course_schedule_fall_2017 [2017/10/27 12:47] – [References] edit |
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| * [[http://ieeexplore.ieee.org/document/7783759 |[Ham16]]] T. J. Ham, et al., "Graphicionado: A High-Performance and Energy Efficient Accelerator for Graph Analytics," Proceedings of MICRO, 2016. | * [[http://ieeexplore.ieee.org/document/7783759 |[Ham16]]] T. J. Ham, et al., "Graphicionado: A High-Performance and Energy Efficient Accelerator for Graph Analytics," Proceedings of MICRO, 2016. |
| * [[http://dl.acm.org/citation.cfm?id=3021745 |[Han17]]] S. Han, et al., "ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA," Proceedings of ISFPGA, 2017. | * [[http://dl.acm.org/citation.cfm?id=3021745 |[Han17]]] S. Han, et al., "ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA," Proceedings of ISFPGA, 2017. |
| * [[http://dl.acm.org/citation.cfm?id=370535 |[Hartenstein01]]] R. Hartenstein, “Coarse Grain Reconfigurable Architecture,” Proceedings of ASPDAC, 2001. | |
| * [[http://dl.acm.org/citation.cfm?id=2925892 |[Hegarty16]]] J. Hegarty, et al., "Rigel: flexible multi-rate image processing hardware," Proceedings of SIGGRAPH, 2016. | * [[http://dl.acm.org/citation.cfm?id=2925892 |[Hegarty16]]] J. Hegarty, et al., "Rigel: flexible multi-rate image processing hardware," Proceedings of SIGGRAPH, 2016. |
| * [[http://dl.acm.org/citation.cfm?id=3080246 |[Jouppi17]]] N. P. Jouppi, et al., "In-Datacenter Performance Analysis of a Tensor Processing Unit," Proceedings of ISCA, 2017. | * [[http://dl.acm.org/citation.cfm?id=3080246 |[Jouppi17]]] N. P. Jouppi, et al., "In-Datacenter Performance Analysis of a Tensor Processing Unit," Proceedings of ISCA, 2017. |
