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| 18-643_course_schedule_fall_2017 [2017/10/24 23:47] – [Schedule and Lecture Notes] edit | 18-643_course_schedule_fall_2017 [2017/10/27 12:45] – [References] edit |
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| * [[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7086413 |[Trimberger15]]] S. M. Trimberger, “Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology,” Proceedings of the IEEE, March 2015. | * [[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7086413 |[Trimberger15]]] S. M. Trimberger, “Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology,” Proceedings of the IEEE, March 2015. |
| * [[https://dl.acm.org/citation.cfm?id=3050220.3050234 |[[Wang17]]] H. Wang, et al., "P4FPGA: A Rapid Prototyping Framework for P4," Proceedings of SOSR, 2017. | * [[https://dl.acm.org/citation.cfm?id=3050220.3050234 |[[Wang17]]] H. Wang, et al., "P4FPGA: A Rapid Prototyping Framework for P4," Proceedings of SOSR, 2017. |
| * [[http://ieeexplore.ieee.org/document/1395531/?arnumber=1395531 |[Weisz15]]] G. Weisz, et al., "CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing," Proceedings of FPL, 2015. | * [[http://ieeexplore.ieee.org/document/7294017/ |[Weisz15]]] G. Weisz, et al., "CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing," Proceedings of FPL, 2015. |
| * [[http://ac.els-cdn.com/S0141933108001038/1-s2.0-S0141933108001038-main.pdf?_tid=bbf45bee-954a-11e7-bf1b-00000aacb362&acdnat=1504953567_b2447610e91a6e26c21bc141e06ad029 |[Zain-ul-Abdin09]]] Zain-ul-Abdin, et al., "Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing," Microprocessors and Microsystems, Volume 33, Issue 3, May 2009. | * [[http://ac.els-cdn.com/S0141933108001038/1-s2.0-S0141933108001038-main.pdf?_tid=bbf45bee-954a-11e7-bf1b-00000aacb362&acdnat=1504953567_b2447610e91a6e26c21bc141e06ad029 |[Zain-ul-Abdin09]]] Zain-ul-Abdin, et al., "Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing," Microprocessors and Microsystems, Volume 33, Issue 3, May 2009. |
| * [[http://dl.acm.org/citation.cfm?id=2689060 |[Zhang15]]] C. Zhang, et al., "Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks," Proceedings of ISFPGA, 2015. | * [[http://dl.acm.org/citation.cfm?id=2689060 |[Zhang15]]] C. Zhang, et al., "Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks," Proceedings of ISFPGA, 2015. |
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