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| 18-643_course_schedule_fall_2016 [2019/07/05 15:42] – edit | 18-643_course_schedule_fall_2016 [2021/11/22 03:41] – edit |
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| ==== Schedule and Lecture Notes ==== | ==== Schedule and Lecture Notes ==== |
| ^ Week ^ Date ^ L# ^ Topic ^ Readings ^ Lab ^ | ^ Week ^ Date ^ L# ^ Topic ^ Readings ^ Lab ^ |
| | 1 | 8/30 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L01.pdf |L1]] | Introduction | 1st-Half Kick Off: [Trimberger15] | Lab 0: Warm-Up | | | 1 | 8/30 | [[https://users.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L01.pdf |L1]] | Introduction | 1st-Half Kick Off: [Trimberger15] | Lab 0: Warm-Up | |
| | | 9/1 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L02.pdf |L2]] | FPGA Basics | RC Ch 1\\ (skim RC Ch 13,14) | | | | | 9/1 | [[https://users.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L02.pdf |L2]] | FPGA Basics | RC Ch 1\\ (skim RC Ch 13,14) | | |
| | 2 | 9/6 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L03.pdf |L3]] | FPGA Less Basic | (skim [Ahmed16]) | | | | 2 | 9/6 | [[https://users.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L03.pdf |L3]] | FPGA Less Basic | (skim [Ahmed16]) | | |
| | | 9/8 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L04.pdf |L4]] | SoC FPGAs | ZB Ch 2\\ (skim ZB Ch 3,10)] | | | | | 9/8 | [[https://users.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L04.pdf |L4]] | SoC FPGAs | ZB Ch 2\\ (skim ZB Ch 3,10)] | | |
| | 3 | 9/13 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L05.pdf |L5]] | Design Metrics | read H&P chapter on performance if you haven't\\ read for later [Kung86][Shao14]| Lab 1: Vivado SoC | | | 3 | 9/13 | [[https://users.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L05.pdf |L5]] | Design Metrics | read H&P chapter on performance if you haven't\\ read for later [Kung86][Shao14]| Lab 1: Vivado SoC | |
| | | 9/15 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L06.pdf |L6]] | Hard vs Soft Logic | (skim [Kuon06][Chung10][Papamichael12]) | | | | | 9/15 | [[https://users.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L06.pdf |L6]] | Hard vs Soft Logic | (skim [Kuon06][Chung10][Papamichael12]) | | |
| | 4 | 9/20 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L07.pdf |L7]] | Structural RTL | HDL Compiler for Verilog Reference Manual\\ Vivado Design Suite User Guide: Synthesis (UG901)| | | | 4 | 9/20 | [[https://users.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L07.pdf |L7]] | Structural RTL | HDL Compiler for Verilog Reference Manual\\ Vivado Design Suite User Guide: Synthesis (UG901)| | |
| | | 9/22 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L08.pdf |L8]] | Abstract Models | (skim RC Ch5,8,9,10) | | | | | 9/22 | [[https://users.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L08.pdf |L8]] | Abstract Models | (skim RC Ch5,8,9,10) | | |
| | 5 | 9/27 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L09.pdf |L9]] | C-to-HW | [Edwards05] (skim IEEE Design & Test of Computers Issue 4, July-Aug. 2009\\ RC Ch7, ZB Ch 14) | Lab 2: Vivado HLS | | | 5 | 9/27 | [[https://users.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L09.pdf |L9]] | C-to-HW | [Edwards05] (skim IEEE Design & Test of Computers Issue 4, July-Aug. 2009\\ RC Ch7, ZB Ch 14) | Lab 2: Vivado HLS | |
| | | 9/29 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L10.pdf |L10]] | Vivado HLS | ZB Ch 15\\ Vivado Design Suite User Guide: High-Level Synthesis (UG902) | | | | | 9/29 | [[https://users.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L10.pdf |L10]] | Vivado HLS | ZB Ch 15\\ Vivado Design Suite User Guide: High-Level Synthesis (UG902) | | |
| | 6 | 10/4 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L11.pdf |L11]] | Altera OpenCL | RC Ch 10\\ (skim Altera SDK for OpenCL: Programming Guide) | | | | 6 | 10/4 | [[https://users.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L11.pdf |L11]] | Altera OpenCL | RC Ch 10\\ (skim Altera SDK for OpenCL: Programming Guide) | | |
| | | 10/6 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L12.pdf |L12]] | Domain-Specific HLS | (skim [Milder12] [[http://www.spiral.net/hardware/dftgen.html |Spiral DFTgen]]) | | | | | 10/6 | [[https://users.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L12.pdf |L12]] | Domain-Specific HLS | (skim [Milder12] [[http://www.spiral.net/hardware/dftgen.html |Spiral DFTgen]]) | | |
| | 7 | 10/11 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L13.pdf |L13]] | FPGA Memory Architecture | | Lab 3: HW Accelerate | | | 7 | 10/11 | [[https://users.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L13.pdf |L13]] | FPGA Memory Architecture | | Lab 3: HW Accelerate | |
| | | 10/13 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L14.pdf |L14]] | CoRAM FPGA Computing Abstraction | [Chung11][Weisz15] | | | | | 10/13 | [[https://users.ece.cmu.edu/~jhoe/course/ece643/F16handouts/L14.pdf |L14]] | CoRAM FPGA Computing Abstraction | [Chung11][Weisz15] | | |
| | 8 | 10/18 | ^ Midterm 1 | 2nd-Half Kick Off: [Tessier15] (skim [DeHon15]) | | | | 8 | 10/18 | ^ Midterm 1 | 2nd-Half Kick Off: [Tessier15] (skim [DeHon15]) | | |
| | | 10/20 | L15 | Partial Reconfiguration\\ **Guest Lecturer: Marie Nguyen** | | | | | | 10/20 | L15 | Partial Reconfiguration\\ **Guest Lecturer: Marie Nguyen** | | | |
| * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5446252 |[Brewer10]]] T. M. Brewer, “Instruction Set Innovations for the Convey HC-1 Computer,” IEEE Micro, March-April 2010. | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5446252 |[Brewer10]]] T. M. Brewer, “Instruction Set Innovations for the Convey HC-1 Computer,” IEEE Micro, March-April 2010. |
| * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1310240 |[Burger04]]] D. Burger, et al., "Scaling to the end of silicon with EDGE architectures," IEEE Computer, July 2004. | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1310240 |[Burger04]]] D. Burger, et al., "Scaling to the end of silicon with EDGE architectures," IEEE Computer, July 2004. |
| * [[https://www.ece.cmu.edu/~jhoe/course/ece643/temp/1b_2.pdf |[Caufield16]]] A. Caulfield, et al., "A Cloud-Scale Acceleration Architecture," MICRO, October 2016. | * [[https://users.ece.cmu.edu/~jhoe/course/ece643/temp/1b_2.pdf |[Caufield16]]] A. Caulfield, et al., "A Cloud-Scale Acceleration Architecture," MICRO, October 2016. |
| * [[http://legup.eecg.utoronto.ca/ASAP_2016.pdf |[Choi16]]] J. Choi, et al., "A Unified Software Approach to Specify Pipeline and Spatial Parallelism in FPGA Hardware," Proceedings of ASAP, 2016. | * [[http://legup.eecg.utoronto.ca/ASAP_2016.pdf |[Choi16]]] J. Choi, et al., "A Unified Software Approach to Specify Pipeline and Spatial Parallelism in FPGA Hardware," Proceedings of ASAP, 2016. |
| * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5695539 |[Chung10]]] E. S. Chung, et al., “Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?” MICRO, 2010. | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5695539 |[Chung10]]] E. S. Chung, et al., “Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?” MICRO, 2010. |
| * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6927488 |[Fleming14]]] K. Fleming, et al., “The LEAP FPGA Operating System,” FPL, 2014. | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6927488 |[Fleming14]]] K. Fleming, et al., “The LEAP FPGA Operating System,” FPL, 2014. |
| * [[http://ieeexplore.ieee.org/document/6927498/?arnumber=6927498 |[Goeders14]]] J. Goeders, et al., "Effective FPGA debug for high-level synthesis generated circuits," Proceedings of FPL, 2014. | * [[http://ieeexplore.ieee.org/document/6927498/?arnumber=6927498 |[Goeders14]]] J. Goeders, et al., "Effective FPGA debug for high-level synthesis generated circuits," Proceedings of FPL, 2014. |
| * [[https://www.ece.cmu.edu/~jhoe/course/ece643/temp/7_1.pdf |[Ham16]]] T. J. Ham, et al., "Graphicionado: A High-Performance and Energy Efficient Accelerator for Graph Analytics," MICRO 2016. | * [[https://users.ece.cmu.edu/~jhoe/course/ece643/temp/7_1.pdf |[Ham16]]] T. J. Ham, et al., "Graphicionado: A High-Performance and Energy Efficient Accelerator for Graph Analytics," MICRO 2016. |
| * [[http://dl.acm.org/citation.cfm?id=370535 |[Hartenstein01]]] R. Hartenstein, “Coarse Grain Reconfigurable Architecture,” ASPDAC, 2001. | * [[http://dl.acm.org/citation.cfm?id=370535 |[Hartenstein01]]] R. Hartenstein, “Coarse Grain Reconfigurable Architecture,” ASPDAC, 2001. |
| * [[http://dl.acm.org/citation.cfm?id=2925892 |[Hegarty16]]] J. Hegarty, et al., "Rigel: flexible multi-rate image processing hardware," Proceedings of SIGGRAPH, 2016. | * [[http://dl.acm.org/citation.cfm?id=2925892 |[Hegarty16]]] J. Hegarty, et al., "Rigel: flexible multi-rate image processing hardware," Proceedings of SIGGRAPH, 2016. |
| * [[https://www.ece.cmu.edu/~jhoe/course/ece643/temp/Hegde16.pdf |[Hegde16]]] G Hegde, et al., "CaffePresso: An Optimized Library for Deep Learning on Embedded Accelerator-based platforms," CODES+ISSS, 2016. | * [[https://users.ece.cmu.edu/~jhoe/course/ece643/temp/Hegde16.pdf |[Hegde16]]] G Hegde, et al., "CaffePresso: An Optimized Library for Deep Learning on Embedded Accelerator-based platforms," CODES+ISSS, 2016. |
| * [[http://dl.acm.org/citation.cfm?id=2145728 |[Kirchgessner12]]] R. Kirchgessner, et al., “VirtualRC: a Virtual FPGA Platform for Applications and Tools Portability,” ISFPGA, 2012. | * [[http://dl.acm.org/citation.cfm?id=2145728 |[Kirchgessner12]]] R. Kirchgessner, et al., “VirtualRC: a Virtual FPGA Platform for Applications and Tools Portability,” ISFPGA, 2012. |
| * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4068926 |[Kuon06]]] I. Kuon and J. Rose, “Measuring the Gap between FPGAs and ASICs,” ISFPGA, 2006. | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4068926 |[Kuon06]]] I. Kuon and J. Rose, “Measuring the Gap between FPGAs and ASICs,” ISFPGA, 2006. |
