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18-643_course_schedule_fall_2016 [2017/09/29 14:11] – external edit 127.0.0.118-643_course_schedule_fall_2016 [2019/07/05 15:42] – edit
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 | 10 | 11/1 | L16 | [[http://www.hotchips.org/wp-content/uploads/hc_archives/hc21/3_tues/HC21.25.500.ComputingAccelerators-Epub/HC21.25.526.Brewer-Convey-HC1-Instruction-Set.pdf |Convey]] and [[https://harnesscloud.github.io/2015-07-15-feltham/maxeler/CodeCarpentry-MaxelerDataflow1.pdf |Maxeler]] | Review [Brewer10] or [Pell13] | | | 10 | 11/1 | L16 | [[http://www.hotchips.org/wp-content/uploads/hc_archives/hc21/3_tues/HC21.25.500.ComputingAccelerators-Epub/HC21.25.526.Brewer-Convey-HC1-Instruction-Set.pdf |Convey]] and [[https://harnesscloud.github.io/2015-07-15-feltham/maxeler/CodeCarpentry-MaxelerDataflow1.pdf |Maxeler]] | Review [Brewer10] or [Pell13] | |
 |    | 11/3 | L17 | FPGAs in Datacenter ([[http://www.hotchips.org/wp-content/uploads/hc_archives/hc26/HC26-12-day2-epub/HC26.12-5-FPGAs-epub/HC26.12.520-Recon-Fabric-Pulnam-Microsoft-Catapult.pdf |Catapult]])\\ **Guest Lecturer: Derek Chiou (MSR)** | Review [Putnam14] or [Caulfield16] | |  |    | 11/3 | L17 | FPGAs in Datacenter ([[http://www.hotchips.org/wp-content/uploads/hc_archives/hc26/HC26-12-day2-epub/HC26.12-5-FPGAs-epub/HC26.12.520-Recon-Fabric-Pulnam-Microsoft-Catapult.pdf |Catapult]])\\ **Guest Lecturer: Derek Chiou (MSR)** | Review [Putnam14] or [Caulfield16] | | 
-| 11 | 11/8 | L18 | Cache Coherent FPGAs ([[http://www.nallatech.com/wp-content/uploads/Ent2014-CAPI-on-Power8.pdf |IBM CAPI]], [[http://www.ece.cmu.edu/~calcm/carl/lib/exe/fetch.php?media=carl2012_oliver_slides.pdf |Intel QPI]]) | Review [Oliver11] or [Stuecheli15] | | +| 11 | 11/8 | L18 | Cache Coherent FPGAs ([[http://www.nallatech.com/wp-content/uploads/Ent2014-CAPI-on-Power8.pdf |IBM CAPI]], [[http://research.ece.cmu.edu/~calcm/carl/lib/exe/fetch.php?media=carl2012_oliver_slides.pdf |Intel QPI]]) | Review [Oliver11] or [Stuecheli15] | | 
 |    | 11/10 | L19 | Coarse-Grained Reconfigurable Array ([[http://www.hotchips.org/wp-content/uploads/hc_archives/hc17/3_Tue/HC17.S5/HC17.S5T2.pdf |TRIPS]], [[http://www.hotchips.org/wp-content/uploads/hc_archives/hc13/3_Tue/22mit.pdf |RAW]]) | Review [Taylor02] or [Burger04]  (skim [Hartenstein01] ) | | |    | 11/10 | L19 | Coarse-Grained Reconfigurable Array ([[http://www.hotchips.org/wp-content/uploads/hc_archives/hc17/3_Tue/HC17.S5/HC17.S5T2.pdf |TRIPS]], [[http://www.hotchips.org/wp-content/uploads/hc_archives/hc13/3_Tue/22mit.pdf |RAW]]) | Review [Taylor02] or [Burger04]  (skim [Hartenstein01] ) | |
 | 12 | 11/15 | L20 | High-Level Synthesis | Review [Choi16] or [Goeders14] | | | 12 | 11/15 | L20 | High-Level Synthesis | Review [Choi16] or [Goeders14] | |
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   * [[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7086413 |[Trimberger15]]] S. M. Trimberger, “Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology,” Proceedings of the IEEE, March 2015.   * [[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7086413 |[Trimberger15]]] S. M. Trimberger, “Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology,” Proceedings of the IEEE, March 2015.
   * [[http://ieeexplore.ieee.org/document/7161556/ |[Wang15]]] K. Wang, et al., "Association Rule Mining with the Micron Automata Processor," Proceedings of IPDPS, 2015.     * [[http://ieeexplore.ieee.org/document/7161556/ |[Wang15]]] K. Wang, et al., "Association Rule Mining with the Micron Automata Processor," Proceedings of IPDPS, 2015.  
-  * [[http://ieeexplore.ieee.org/document/1395531/?arnumber=1395531 |[Weisz15]]] G. Weisz, et al., "CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing," Proceedings of FPL, 2015.+  * [[http://ieeexplore.ieee.org/document/7294017/ |[Weisz15]]] G. Weisz, et al., "CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing," Proceedings of FPL, 2015.
   * [[http://dl.acm.org/citation.cfm?id=2689060 |[Zhang15]]] C. Zhang, et al., "Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks," Proceedings of FPGA, 2015.   * [[http://dl.acm.org/citation.cfm?id=2689060 |[Zhang15]]] C. Zhang, et al., "Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks," Proceedings of FPGA, 2015.