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| — | 18-643_course_schedule_fall_2015 [2017/09/29 14:11] – external edit 127.0.0.1 |
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| | ====== 18-643 Course Schedule, Fall 2015====== |
| | |
| | * Lecture notes are posted within 24 hours after the lecture |
| | * Reading assignments are to be completed BEFORE coming to class. |
| | * RC=//Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation// by Scott Hauck and Andre DeHon. |
| | * ZB=//The Zynq Book// by Louise H. Crockett, et al. |
| | * [[18-643_course_schedule_fall_2015#references |Additional papers]] |
| | * There are 4 two-week-long do-at-home labs in the first half of the semester. There is a single project for the second half of the semester. |
| | * Please note the dates for midterms and required in-class presentations. |
| | * (Go to [[18-643_reconfigurable_logic |the Course Home Page]]) |
| | * (Go to [[https://blackboard.andrew.cmu.edu/ |Blackboard]]) |
| | \\ |
| | |
| | ==== Schedule and Lecture Notes ==== |
| | ^ Week ^ Date ^ L# ^ Topic ^ Readings ^ Lab ^ |
| | | 1 | 9/1 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F15handouts/L01.pdf |L1]] | Introductions | (skim [Trimberger15]) | Lab 0: Warm-Up | |
| | | | 9/3 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F15handouts/L02.pdf |L2]] | FPGA Basics | RC Ch 1\\ (skim RC Ch 13,14) | | |
| | | 2 | 9/8 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F15handouts/L03.pdf |L3]] | FPGA Less Basic | (skim [DeHon15]) | | |
| | | | 9/10 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F15handouts/L04.pdf |L4]] | SoC FPGAs | ZB Ch 2\\ (skim ZB Ch 3,10)] | | |
| | | 3 | 9/15 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F15handouts/L05.pdf |L5]] | Zedboard | ZB Ch 6,8 | Lab 1: Vivado SoC | |
| | | | 9/17 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F15handouts/L06.pdf |L6]] | Performance | read H&P chapter on performance if you haven't\\ read for later [Kung86][Shao14]| | |
| | | 4 | 9/22 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F15handouts/L07.pdf |L7]] | Hard vs Soft Logic | (skim [Kuon06][Chung10][Papamichael12]) | | |
| | | | 9/24 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F15handouts/L08.pdf |L8]] | Structural RTL | HDL Compiler for Verilog Reference Manual\\ Vivado Design Suite User Guide: Synthesis (UG901)| | |
| | | 5 | 9/29 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F15handouts/L09.pdf |L9]] | Abstract Models | (skim RC Ch5,8,9,10) | Lab 2: Vivado HLS | |
| | | | 10/1 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F15handouts/L10.pdf |L10]] | C-to-HW | (skim IEEE Design & Test of Computers Issue 4, July-Aug. 2009\\ RC Ch7, ZB Ch 14) | | |
| | | 6 | 10/6 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F15handouts/L11.pdf |L11]] | Vivado HLS | ZB Ch 15\\ Vivado Design Suite User Guide: High-Level Synthesis (UG902) | | |
| | | | 10/8 | L12 | Confessions of a User (Marie Nguyen) | | | |
| | | 7 | 10/13 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F15handouts/L13.pdf |L13]] | Spiral "HLS" | (skim [Milder12][Akin12]) | Lab 3: HW Accelerate | |
| | | | 10/15 | ^ Midterm 1 | | | |
| | | 8 | 10/20 | L14 | Machine Learning in Data Center (Eric Chung, MSR) | [Ovtcharov15] | | |
| | | | 10/22 | [[https://www.ece.cmu.edu/~jhoe/course/ece643/F15handouts/L15.pdf |L15]] | Reconfigurable Computing | [Tessier15] | | |
| | | | 10/23 | ^ Midsemester Break | | | |
| | | 9 | 10/27 | ^ Term Project Proposal Student Presentations | | Project Start | |
| | | | 10/29 | ^ Term Project Proposal Student Presentations | | | |
| | | 10 | 11/3 | L16 | [[http://www.hotchips.org/wp-content/uploads/hc_archives/hc21/3_tues/HC21.25.500.ComputingAccelerators-Epub/HC21.25.526.Brewer-Convey-HC1-Instruction-Set.pdf |Convey]] and [[https://harnesscloud.github.io/2015-07-15-feltham/maxeler/CodeCarpentry-MaxelerDataflow1.pdf |Maxeler]] | Review [Brewer10] or [Pell13] | | |
| | | | 11/5 | L17 | Cache Coherent FPGAs ([[http://www.nallatech.com/wp-content/uploads/Ent2014-CAPI-on-Power8.pdf |IBM CAPI]], [[http://www.ece.cmu.edu/~calcm/carl/lib/exe/fetch.php?media=carl2012_oliver_slides.pdf |Intel QPI]]) | Review [Oliver11] or [Stuecheli15] | | |
| | | 11 | 11/10 | L18 | [[https://github.com/LEAP-FPGA/leap-documentation/wiki/Talks |LEAP FPGA OS]] (Michael Adler, Intel) | Review [Fleming14] | | |
| | | | 11/12 | L19 | Programming Abstractions ([[http://hpcl.gwu.edu/asap2013/presentations/Virt/Heo_ASAP_2013.pdf|VirtualRC]],[[http://www.ece.cmu.edu/~coram|CoRAM]]) | Review [Chung11] or [Kirchgessner12] | | |
| | | 12 | 11/17 | L20 | FPGAs in Datacenter ([[http://www.hotchips.org/wp-content/uploads/hc_archives/hc26/HC26-12-day2-epub/HC26.12-5-FPGAs-epub/HC26.12.520-Recon-Fabric-Pulnam-Microsoft-Catapult.pdf |Catapult]]) | Review [Putnam14] | | |
| | | | 11/19 | L21 | Coarse-Grained Reconfigurable Array ([[http://www.hotchips.org/wp-content/uploads/hc_archives/hc17/3_Tue/HC17.S5/HC17.S5T2.pdf |TRIPS]], [[http://www.hotchips.org/wp-content/uploads/hc_archives/hc13/3_Tue/22mit.pdf |RAW]]) | Review [Taylor02] or [Burger04] (skim [Hartenstein01] ) | | |
| | | 13 | 11/24 | L22 | Computing Applications | Review one of [Xcell15] | | |
| | | | 11/26 | ^ Thanksgiving | | | |
| | | 14 | 12/1 | ^ Term Project Student Presentations | | | |
| | | | 12/3 | ^ Term Project Student Presentations | | Project End | |
| | | 15 | 12/8 | L23 | slack | | | |
| | | | 12/10 | ^ Midterm 2 | | | |
| | \\ |
| | |
| | ==== References ==== |
| | All of the following references can be found online. Please respect copyrights. CMU students have access to [[http://ieeexplore.ieee.org/Xplore/home.jsp |IEEE Xplore]] and [[ |
| | http://dl.acm.org/ | ACM Digital Library]] from CMU network. |
| | |
| | * [[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6239813 |[Akin12]]] B. Akin, et al., "Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes," FCCM, 2012. |
| | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5446252 |[Brewer10]]] T. M. Brewer, “Instruction Set Innovations for the Convey HC-1 Computer,” IEEE Micro, March-April 2010. |
| | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1310240 |[Burger04]]] D. Burger, et al., "Scaling to the end of silicon with EDGE architectures," IEEE Computer, July 2004. |
| | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5695539 |[Chung10]]] E. S. Chung, et al., “Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?” MICRO, 2010. |
| | * [[http://dl.acm.org/citation.cfm?id=1950435 |[Chung11]]] E. S. Chung, et al., “CoRAM: an in-fabric memory architecture for FPGA-based computing,” ISFPGA 2011. |
| | * [[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7086421 |[DeHon15]]] A. DeHon, "Fundamental Underpinnings of Reconfigurable Computing Architectures," Proceedings of the IEEE, March 2015. |
| | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6927488 |[Fleming14]]] K. Fleming, et al., “The LEAP FPGA operating system,” FPL, 2014. |
| | * [[http://dl.acm.org/citation.cfm?id=370535 |[Hartenstein01]]] R. Hartenstein, “Coarse grain reconfigurable architecture,” ASPDAC, 2001. |
| | * [[http://dl.acm.org/citation.cfm?id=2145728 |[Kirchgessner12]]] R. Kirchgessner, et al., “VirtualRC: a virtual FPGA platform for applications and tools portability,” ISFPGA, 2012. |
| | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4068926 |[Kuon06]]] I. Kuon and J. Rose, “Measuring the gap between FPGAs and ASICs,” ISFPGA, 2006. |
| | * [[http://dl.acm.org/citation.cfm?id=17362 |[Kung86]]] H. T. Kung, "Memory requirements for balanced computer architectures," ISCA 1986. |
| | * [[http://dl.acm.org/citation.cfm?id=2159542.2159547 |[Milder12]]] P. Milder, et al., “Computer Generation of Hardware for Linear Digital Signal Processing Transforms,” ACM TODAES, April 2012. |
| | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6128558 |[Oliver11]]] N. Oliver, et al., “A Reconfigurable Computing System Based on a Cache-Coherent Fabric,” ReConFig, 2011. |
| | * [[http://research.microsoft.com/pubs/240715/CNN%20Whitepaper.pdf |[Ovtcharov15]]] K. Ovtcharov, et al., "Accelerating Deep Convolutional Neural Networks Using Specialized Hardware," Microsoft Research, 2015. |
| | * [[http://dl.acm.org/citation.cfm?id=2145703 |[Papamichael12]]] M. Papamichael, et al., “CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs,” ISFPGA, 2012. |
| | * [[http://link.springer.com/chapter/10.1007%2F978-1-4614-1791-0_25 |[Pell13]]] O. Pell, et al., “Maximum Performance Computing with Dataflow Engines,” in High-Performance Computing Using FPGAs, Springer, 2013. |
| | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6853195 |[Putnam14]]] A. Putnam, et al., “A reconfigurable fabric for accelerating large-scale datacenter services,” ISCA, 2014. |
| | * [[http://dl.acm.org/citation.cfm?id=2665689 |[Shao14]]] Y.S.Shao, et al., “Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures,” ISCA, 2014. |
| | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7029171 |[Stuecheli15]]] J. Stuecheli, et al., “CAPI: A Coherent Accelerator Processor Interface,” IBM Journal of Research and Development , Jan.-Feb. 2015. |
| | * [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=997877 |[Taylor02]] M. B. Taylor, et al., “The Raw microprocessor: a computational fabric for software circuits and general-purpose programs,” IEEE Micro, 2002. |
| | * [[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7086414 |[Tessier15]]] R. Tessier, et al. "Reconfigurable Computing Architectures," Proceedings of the IEEE, March 2015. |
| | * [[http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7086413 |[Trimberger15]]] S. M. Trimberger, “Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology,” Proceedings of the IEEE, March 2015. |
| | * [[http://www.xilinx.com/publications/archives/xcell/Xcell92.pdf |[XCell15]]] XCell Journal, Xilinx, Third Quarter, 2015. |
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