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18-100 Course Schedule, Fall 2012

  • Lecture
    • TR 01:30PM 02:50PM PH 100
  • Recitatations
    • M 11:30AM 12:20PM WEH 4709
    • M 12:30PM 01:20PM WEH 4709
    • M 01:30PM 02:20PM PH A20
    • M 02:30PM 03:20PM WEH 5409
    • M 03:30PM 04:20PM WEH 6423
  • Labs
    • M/T/W/Th 06:30PM 09:20PM HH A101
    • F 01:30PM 04:20PM HH A101


Week Date L# Topic
1 8/28 L1 Introduction, discussion of engineering systems and sub-systems, basic electricity
8/30 L2 Voltage, current, resistance, power, circuit schematic symbols, ground
2 9/4 L3 Power dissipation, Ohm's law, Kirchoff's Voltage and Current Laws, basic circuits
9/6 L4 Series and parallel resistances and combinations, solving circuits using equivalent resistances
3 9/11 L5 Superposition, Thevenin and Norton Equivalents, Source Transformation
9/13 L6 Introduction to capacitors and inductors, impedance, begin 1st order systems
4 9/18 L7 Continue 1st order systems, RC and LR circuits, time and freq. domain
9/20 L8 2nd order systems, LRC circuits, frequency response
5 9/25 L9 CIT Area Talks. Review for Exam I
9/27 L10 Introduction to Operational Amplifiers, open and closed loop gain, op-amp assumptions, inverting and non-inverting amplifier circuits
6 10/2 Exam I
10/4 L11 Buffers, summing and difference circuits, active filters
7 10/9 L12 Introduction to diodes (signal, zener, and LED), basic diode operation, piecewise linear model (PWL) for diodes, rectifiers
10/11 L13 Introduction to transistors, basic transistor operation, piecewise linear model for NPN transistors, common emitter circuits
8 10/16 L14 Common collector transistor circuit and circuits with emitter and collector resistors
10/18 L15 Small signal analysis of transistor circuits, amplifiers
9 10/23 L16 Signals and modulation
10/25 L17 Sampling, analog to digital conversion, quantization, base conversions, binary arithmetic
10 10/30 L18 Finish signal processing concept. Review for Exam II
11/1 L19 Introduction to Computer Systems, begin basic assembly language
11 11/6 Exam II
11/8 L20 Basic assembly language (cont.)
12 11/13 L21 Logic gates, Boolean expressions, DeMorgan's theorems, begin combinational logic circuits
11/15 L22 Combinational logic circuits (cont.), truth tables, digital circuit schematics, two-level circuit representation
13 11/20 L23 Karnaugh maps, adders, multiplexers, de-multiplexers
11/22 bonus Thanksgiving (no class)
14 11/27 L24 Feedback in logic circuits, SR flip-flops, D flip-flops, master-slave edge-triggered flip-flops, sequential logic, state diagrams, state transition tables, begin finite state machine design
11/29 L25 Continue finite state machine design, design of counters, output mapping, sequential logic circuits with external inputs
15 12/4 L26 CIT Area Talks. Review for Exam III
12/6 Exam III
12/17 Final Exam, 8:30a.m.‐11:30a.m.