Yoongu Kim

Ph.D. Candidate (Expected: Summer 2015)
Electrical and Computer Engineering
Carnegie Mellon University


About Me

Since 2008, I have been a Ph.D. student in the ECE department at CMU. Previously, I received my B.S. in electrical engineering from Seoul National University. I am a recipient of Ph.D. fellowships from Samsung (2014-2015), Intel (2013-2014) and the Korea Foundation for Advanced Studies (2008-2013). In the past, I also received a medal from Blizzard Entertainment for playing their computer game too much.


Within the general domain of computer architecture, the focus of my research is on the main memory subsystem. My goal is to improve its performance, energy-efficiency, and reliability. My research has been featured in Google Project Zero, Hacker News, ZDNet, Wired, as well as in Intel/Samsung's Joint White Paper.


Samsung ElectronicsMemory Solutions LaboratoryJune 2013 - September 2013
Research Intern

Intel CorporationMemory Controller TeamMay 2012 - August 2012
Research Intern

IBM T. J. Watson Research CenterJune 2010 - September 2010
Research Intern

FCI (Silicon Motion)In Fulfillment of Military ServiceDecember 2006 - July 2008
Circuit Design Engineer

TopfieldIn Fulfillment of Military ServiceJuly 2005 - November 2006
Hardware Engineer

Tools & Data

ramulator (GitHub): A cycle-accurate DRAM simulator. Accompaniment to "Ramulator: A Fast and Extensible DRAM Simulator" by Kim et al., CAL 2015.

adaptive-latency (Link): Dataset for "Adaptive-Latency DRAM" by Lee et al., HPCA 2015.

rowhammer (GitHub): Memory tester for DRAM disturbance errors. Built on top of Memtest86+ v5.01. Also provides dataset for "Flipping Bits in Memory Without Accessing Them" by Kim et al., ISCA 2014.

retention-fail (Link): Dataset for "DRAM Retention Failures" by Khan et al., SIGMETRICS 2014.


Ramulator: A Fast and Extensible DRAM Simulator
Yoongu Kim, Weikun Yang, Onur Mutlu
IEEE CAL, 2015

Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case
Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Khan, Vivek Seshadri, Kevin Chang, Onur Mutlu
HPCA-21, 2015

Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors
Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu.
ISCA-41, 2014

The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study
Samira Khan, Donghyuk Lee, Yoongu Kim, Alaa Alameldeen, Chris Wilkerson, Onur Mutlu.

Memory Systems
Yoongu Kim and Onur Mutlu
Computing Handbook (Third Edition), 2014. Chapman and Hall/CRC.

Improving DRAM Performance by Parallelizing Refreshes with Accesses
Kevin Chang, Donghyuk Lee, Zeshan Chishti, Chris Wilkerson, Alaa Alameldeen, Yoongu Kim, Onur Mutlu.
HPCA-20, 2014

RowClone: Fast and Efficient In-DRAM Copy and Initialization of Bulk Data
Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry.
MICRO-46, 2013

Linearly Compressed Pages: A Main Memory Compression Framework with Low Complexity and Low Latency
Gennady Pekhimenko, Vivek Seshadri, Yoongu Kim, Hongyi Xin, Onur Mutlu, Michael A. Kozuch, Phillip B. Gibbons, Todd C. Mowry.
MICRO-46, 2013

An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms
Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, Onur Mutlu
ISCA-40, 2013

Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture
Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, Onur Mutlu
HPCA-19, 2013

MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems
Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, Onur Mutlu
HPCA-19, 2013

A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM
Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu
ISCA-39, 2012

Thread Cluster Memory Scheduling
Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter
IEEE Micro, 2011 — One of Eleven "Top Picks from 2010 Computer Architecture Conferences"

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter
MICRO-43, 2010

ATLAS: A Scalable and High-Performance Scheduling Algorithm for Multiple Memory Controllers
Yoongu Kim, Dongsu Han, Onur Mutlu, Mor Harchol-Balter
HPCA-16, 2010 — One of Four "Best Paper Nominees"

"It's dangerous to go alone; take these."

+8 Back Pain Resistance

+12 RSI Resistance; +4 Technical Writing

+19 RSI Resistance; +3 Web Surfing

+23 Noise Resistance; +73% Sanity during Trans-Pacific Flights