Rutenbar Lab Alumni

Former PhD Students
     Dorothy Setliff Knowledge-Based Synthesis of Custom VLSI Router Software , 1989. Currently with IBM, Raleigh, NC
  Ramesh Harjani OASYS: A Framework for Analog Circuit Synthesis , 1989. Currently Professor of Electrical and Computer Engineering, University of Minnesota.
  Saul Kravitz Massively Parallel Switch-Level Simulation: A Feasibility Study , 1989. Currently Director of Software Engineering, J. Craig Venter Institute - Joint Technology Center, Rockville, MD
  Erik Carlson Exploiting Massive Parallelism in VLSI Mask Verification , 1989. Currently Quantitative Analyst and Founder, Beacon Capital Strategies, New York, NY.
  David Garrod Device-Level Routing of Analog Cells in ANAGRAM II , 1991. Currently counsel in Goodwin Procter’s Litigation Department, New York, NY.
  John Cohn Device-Level Placement of Custom Analog Cells in KOAN , 1991. Currently Chief Scientist of Design Automation in the IBM Systems and Technology Group in Burlington, Vermont, and also an IBM Fellow.
  Rajeev Jayaraman Massively Parallel Approaches to VLSI Layout Synthesis , 1991. Currently Director of FPGA Implementation Tools, Xilinx Corp, San Jose, CA
  Balsha Robert Stanisic Power Distribution Synthesis for Analog and Mixed-Signal ASICs in RAIL . Currently with IBM, Rochester MN
  Emil Ochotta Automatic Synthesis of High-Performance Analog Circuits in ASTRX/OBLX , 1994. Currently with Xilinx Inc., San Jose, CA
  Sudip Nag Performance-Directed Simultaneous Place and Route for Field Programmable Gate Arrays, 1995. Currently with Xilinx Corp, San Jose, CA.
  Sujoy Mitra Substrate-Aware Floorplanning for Mixed-Signal ASICs, Ph.D. April 1995. Currently with Xilinx Corp., San Jose, California
  Gary Ellis The Physical Design of Clock Circuits , 1997. Currently with IBM Microelectronics, Austin, TX.
  Bulent Basaran Techniques for Optimal Diffusion Sharing in CMOS Analog and Digital Circuits , 1997. Currently with Magma Design Automation, Inc.,  San Jose, CA.
  Mehmet Aktuna Layout Algorithms for Radio Frequency Circuits , 1999. Currently with Magma Design Automation, Inc.,  San Jose, CA.
  Rony Kay Algorithmic Approach to Design and Optimization of VLSI Interconnect , 1999. Currently Founder and CEO of cPacket Networks, Mountain View, CA.
  Pascal Meier Analysis and Design of Low-Power Multipliers , 1999. Currently with Intel, Santa Clara, CA
  Michael Krasnicki A Methodology for Distributed Simulation-Based Synthesis of Custom Analog Circuits , 2000. Currently with Texas Instruments, Dallas TX
  Rodney Phelps Analog Circuit Synthesis in an Industrial Design Flow , 2001. Currently with Cadence Design Systems (formerly Neolinear), Pittsburgh, PA
  Gi-Joon Nam A Boolean Layout Approach and Its Application to FPGA Routing, University of Michigan, Dept. of EECS, co-advised with UM Prof. Karem Sakallah. Currently with IBM Austin Research Labs, Austin TX.
  Prakash Gopalakrishnan Direct Transistor Level Layout of Digital Blocks , 2003. Currently with Cadence Design Systems (formerly Neolinear), Pittsburgh, PA
  Hui Xu subSAT: A Formulation For Relaxed Boolean Satisfiability and its Applications , 2004. Currently with Xilinx Corp, San Jose CA
  Hongzhou Liu Macromodeling by Datamining in Large Analog Design Spaces , 2004. Currently with Cadence Design Systems (formerly Neolinear), Pittsburgh, PA
  Claire Fang Fang Probabilistic Interval Valued Computation: Representing and Reasoning about Uncertainty in DSP and VLSI Design, 2005. Currently with Microsoft, Seattle WA.
  Saurabh Tiwary Scalable Trajectory Methods for On Demand Analog Macromodel Extraction, 2006. Currently with Cadence Berkeley Labs, Berkeley CA.
  Zhong Xiu The Design and Implementation of a Large-Scale Placer Based on Grid-Warping, 2006. Currently with AMD, Sunnyvale CA.
  James D. Ma An Interval Valued Computation Methodology for Statistical Retrofitting of Existing Circuit and Technology CAD Tools, 2006. Currently with Graham Capital Management, Rowayton, CT.
  Edward C. Lin A High Performance Custom Hardware Backend Search Engine for a Speech Recognition System, December 2007. Currently Post-Doctoral research staff, Dept of ECE, Carnegie Mellon University.
  Amith Singhee Novel Algorithms for Fast Statistical Analysis of Scaled Circuits, January 2008. Currently with IBM T.J. Watson Research Center, Yorktown Heights, NY.

Former Master's Students

  1. Saul Kravitz, 1986
  2. Erik Carlson, 1986
  3. Rajeev Jayaraman, 1987
  4. Emil Ochotta, 1989
  5. Dean Grannes, 1990
  6. John Lee 1990
  7. Sudip Nag, 1992
  8. Sujoy Mitra, 1992
  9. Bulent Basaran, 1993
  10. K.K. Paul Lai 1994
  11. William E. Jones III, 1996
  12. R. Glenn Wood, 1996
  13. Mehmet Aktuna, 1996
  14. Ashish Kholi (Mechanical Engineering, advised jointly with Prof. Jon Cagan ), 1996
  15. Michael Krasnicki, 1997
  16. Christopher Dunn, 1997
  17. Brian Bernberg, 1998
  18. Prakash Gopalakrishnan, 1999
  19. Clair Fang Fang, 2001
  20. Suzanne Fowler, 2001
  21. Amit Singhee, 2002
  22. Saurabh Tiwary, 2002
  23. Zhong Xiu, 2003
  24. Dong Chen, 2003
  25. Edward Lin, 2003
  26. Smriti Gupta, 2004
  27. Patrick Bourke, 2004
  28. Sonia Singhal, 2007
  29. Jeffrey Johnston, 2008
  30. Pragati Tiwary, 2008