Low Density Parity Check (LDPC) Codes Research Interests

Turbo codes, or parallel-concatenated codes, originally proposed by Berrou et al. in 1993, were shown to achieve remarkable, near-Shannon capacity performance for additive, white Gaussian noise (AWGN) channels. However, the iterative soft decoding algorithm for turbo codes is too complex to achieve the near Gbps data rates needed in hard disk drives. Another class of codes called Low-Density Parity-Check (LDPC) codes (originally invented by R. Gallagher in early 1960’s), appear to exhibit similar error correction performance, although their decoding is usually simpler than that of the original turbo codes. LDPC codes are block codes with a very sparse parity check matrix. For example, a popular choice for the parity check matrix is a matrix with 512 rows and 4608 columns (representing a rate 8/9 code) with perhaps three to six nonzero values per column. Several simulation studies indicate that LDPC codes may be able to offer about 3 to 5 dB SNR improvement over uncoded partial response maximum likelihood (PRML) method.

Although LDPC code decoding is significantly simpler than the original Turbo codes, it is still too complex to achieve the near Gbps data rates needed in hard disk drives. We are investigating the following topics with the goals of improving the performance and reducing the complexity of the decoding.

· Using codes with column weight of 2, thus reducing the number of memory accesses,

· Using structured parity check matrices in place of random matrices, and

· Eliminating short cycles in the factor graph representing the LDPC code in order to improve the convergence properties of the iterative soft decoder.

Our studies indicate that, for low SNRs, column weight 2 LDPC codes perform as well as LDPC codes with column weight of 3 and in fact may be more compatible with outer error correcting codes such as Reed Solomon codes. We are currently investigating the application of LDPC codes to magnetic tape recording channels. We are closely working with Prof. Herman Schmit of ECE Dept. at CMU to develop FPGA hardware for LDPC decoding.

References:

H. Song, B.V.K. Vijaya Kumar, E. Kurtas, Y. Yuan, L. McPheters and S. McLaughlin, “Iterative decoding for partial response (PR), equalized, magneto-optical data storage channels,” IEEE Journal on Selected Areas of Communications, Vol. 19, 774-782, April 2001.

· H. Song, J. Liu, and B. V. K. Vijaya Kumar, “Low complexity LDPC codes for partial response channels,” Globecom’2002, Taipei, Taiwan, November 2002.