5053952 : Stack-memory-based writable instruction set computer having a single data bus

What we claim is:

• 1. A writable instruction set computer comprising:
  • data bus means for transferring data having a predetermined number of bits;
  • addressable and writable main program memory means coupled to said data bus means for storing macrocode, including instructions having the predetermined number of bits, and for storing data from and loading stored data onto said data bus means;
  • memory address logic means coupled to said data bus means and said main program memory means for addressing said main program memory means;
  • addressble and writable micro-program memory means coupled to said main program memory means for storing microcode instructions addressed by the macrocode instructions;
  • arithmetic logic unit (ALU) means coupled to said data bus means for performign operations on data received from said data bus means as defined by the microcode stored in said micro-program memory means;
  • data stack memory means coupled to said data bus means for storing data received from said data bus means for use during program execution;
  • return stack memory means physically separate from said main memory means, and coupled to said data bus means and to said memory address logic means for storing subroutine return address used during program execution, said memory address logic means addressing said main program memory means with the subroutine return address stored in said return stack memory means while said ALU means performs operations on data transferred from said data stack memory means on said data bus means;
  • clock means for generating a cyclic clock signal; and
  • execution control logic means coupled to said micro-program memory means, ALU means, data stack memory means, return stack memory means, data bus means, and clock means for executing the microcode instructions, including performing only one data transfer on said data bus means for each clock signal cycle;
  • said data bus means providing only one communication path for transferring bidirectionally data between said ALU means, said data stack memory means and said main program memory means.
• 2. A computer according to claim 1 wherein said main program memory means stores each instruction as the combination of an opcode and a main program memory address.
• 3. A computer according to claim 2 wherein said address included in said instruction comprises the address of the location of the succeeding instruction in said main program memory.
• 4. A computer according to claim 3 wherein said execution control logic means is further for executing the operation specified by the opcode of a current macrocode instruction while, simultaneously with the operation executing, said memory address logic means fetches the macrocode instruction corresponding to the address included in the current macrocode instruction.
• 5. A computer according to claim 4 wherein said main program memory means further stores for a machine language program instruction, an indicator indicating whether the succeeding operation is a subroutine return, and said memory address logic means is further responsive to address information received from said stack memory means for executing a subroutine return simultaneously with the executing of the current operation, when the indicator indicates that the next operation is a subroutine return.
• 6. A computer according to claim 5 wherein said main program memory means stores a condition code having one of a plurality of values including a predetermined value, and a macrocode instruction comprises a conditional branch opcode requiring execution of a subroutine call if the value of the condition code is the predetermined value, and a subroutine call address, said memory address logic means further executing the subroutine call while said execution control logic means executes the conditional branch opcode, said memory address logic means being responsive to said execution control logic means for aborting the execution of the subroutine call if the value of the condition code is not the predetermined value.
• 7. A computer according to claim 1 wherein said ALU means comprises first and second input ALU ports and an output ALU port, said computer further comprising transparent latch means having an input latch port coupled to said data bus means and an output latch port coupled to said first input ALU port, said latch means being controllable for either transferring data input on said input latch port to said output latch port or retaining data input on said input latch port without it appearing on said output latch poret, and data register means having a register input port coupled to to said output ALU port and a register output port coupled to said second input ALU port and to said data bus means, said transparent latch means being for storing temporarily data received from said data bus means while data stored in said data register means is output to said data bus means.
• 8. A computer according to claim 1 wherein each macrocode instruction includes an opcode, and further comprising:
  • data stack pointer means coupled to said data bus means and said data stack memory means for only storing one pointer pointing to an element in said data stack memory mean,s wherein said execution control logic means is further for setting the pointer to point to any element in said data stack memory means without altering the contents of said stack memory means, the one pointer being the only means for accessing an element in said data stack memory means; and
  • interrupt means coupled to said execution control logic means, and responsive to interrupt signals for generating an interrupt opcode when an interrupt signal indicates that the program execution is to be interrupted;
  • said execution control logic means being responsive to the interrupt opcode for itnerrupting program execution by isnerting the interrupt opcode in place of the next macrocode opcode, and thereby interrupting the program execution only when a next macrocode opcode is to be executed by said execution control logic means, said execution control logic means further controlling execution of the macrocode such that the pointer stored in said data stack pointer means is set to point to a predetermined data stack element prior to executing each new macrocode opcode, whereby the pointer can be changed to point to different data stack elements during execution of a macrocode opcode without altering the contents of said data stack memory means.
• 9. A writable instruction set computer comprising:
  • bus means;
  • addressable and writable main program memory means coupled to said bus means for storing macrocode including opcodes, and data, and for loading stored data onto said bus means;
  • memory address logic means coupled to said bus means and said main program memory means for addressing said main program memory means;
  • addressable and writable micro-program memory means coupled to said main program memory means for storing microcode addressed by the macrocode opcodes;
  • arithmetic logic unit (ALU) means coupled to said bus means for performing operations on data from said bus means as defined by microcode stored in said micro-program memory means;
  • data stack memory means coupled to said bus means for storing data used during opcode execution;
  • execution control logic means coupled to said main program memory means, said bus means and said micro-program memory means, and responsive to instructions received from said main program memory means for executing the macrocode;
  • data stack pointer means coupled to said bus means and said data stack memory means for only storing one pointer pointing to an element in said data stack memory means, wherein said execution control logic means is further for setting the pointer to point to any element in said data stack memory means without altering the contents of said data stack memory means, the one poitner being the only means for accessing an element in said data stack memory means; and
  • interrupt means coupled to said execution control logic means, and responsive to interrupt signals for generating an interrupt opcode when an interrupt signal indicates that the program execution is to be interrupted;
  • said execution control logic means bieng responsive to the itnerrupt opcode for interrupting program execution by inserting the interrupt opcode in place of the next macrocode opcode, and thereby interrupting the program execution only when a next macrocode opcode is to be executed by said execution control logic means, said execution control logic means further controlling execution of the macrocode such that the pointer stored in said data stack pointer means is set to point to a predetermined data stack element prior to executing each new macrocode opcode, whereby the pointer can be changed to point to different data stack elements during execution of a macrocode opcode without altering the contents of said data stack memory means.