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18-100 Introduction to ECE Course Description

Blackboard Site



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	*  Lecture
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	*  Recitatations 
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		*  M 	12:30PM 	01:20PM 	WEH 4709
		*  M 	01:30PM 	02:20PM 	PH A20
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	*  Recitatations 
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		*  18-100 Introduction to ECE Course Description
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Reading assignments are to be completed BEFORE coming to class.  (P&amp;H=The Hardware/Software
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        <description>18-447 Course Schedule, Spring 2011  (**Not Most Recent**)

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        <description>18-447 Course Schedule, Spring 2016  (**Not Most Recent**)

Reading assignments are to be completed BEFORE coming to class.  (P&amp;H=The Hardware/Software
Interface, Fifth Edition by Patterson and Hennessy, Morgan Kaufmann/Elsvier.) You may also find it 
helpful to preview lecture notes from</description>
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        <description>18-447 Course Schedule, Spring 2017  (**Not Most Recent**)

Reading assignments are to be completed BEFORE coming to class.  (P&amp;H=The Hardware/Software
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        <description>18-447 Course Schedule, Spring 2018  (**Not Most Recent**)

Reading assignments are to be completed BEFORE coming to class.  (New for S18: P&amp;H=Computer Organization and Design RISC-V Edition: The Hardware Software Interface, 1st Edition by Patterson and Hennessy, Morgan Kaufmann/Elsvier.) You may also find it 
helpful to preview lecture notes from</description>
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        <title>18-447_course_schedule_spring_2019</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-447_course_schedule_spring_2019&amp;rev=1704291693&amp;do=diff</link>
        <description>18-447 Course Schedule, Spring 2019  (**Not Most Recent**)

Reading assignments are to be completed BEFORE coming to class.  (P&amp;H=Computer Organization and Design RISC-V Edition: The Hardware Software Interface, 1st Edition by Patterson and Hennessy, Morgan Kaufmann/Elsvier.) You may also find it 
helpful to preview lecture notes from</description>
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        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>18-447_course_schedule_spring_2020</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-447_course_schedule_spring_2020&amp;rev=1704291552&amp;do=diff</link>
        <description>18-447 Course Schedule, Spring 2020  (**Not Most Recent**)

Reading assignments are to be completed BEFORE coming to class.  (P&amp;H=Computer Organization and Design RISC-V Edition: The Hardware Software Interface, 1st Edition by Patterson and Hennessy, Morgan Kaufmann/Elsvier.) You may also find it 
helpful to preview lecture notes from</description>
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        <title>18-447_course_schedule_spring_2021</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-447_course_schedule_spring_2021&amp;rev=1704291497&amp;do=diff</link>
        <description>18-447 Course Schedule, Spring 2021  (**Not Most Recent**)

Reading assignments are to be completed BEFORE coming to class.  (P&amp;H=Computer Organization and Design RISC-V Edition: The Hardware Software Interface, 2nd Edition by Patterson and Hennessy, Morgan Kaufmann/Elsvier.) You may also find it 
helpful to preview lecture notes from</description>
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        <description>18-447 Course Schedule, Spring 2022 (**Not Most Recent**)

Reading assignments are to be completed BEFORE coming to class.  (P&amp;H=Computer Organization and Design RISC-V Edition: The Hardware Software Interface, 2nd Edition by Patterson and Hennessy, Morgan Kaufmann/Elsvier.) There will be additional assigned readings from research papers.</description>
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        <dc:date>2024-01-03T14:07:11+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>18-447_course_schedule_spring_2023</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-447_course_schedule_spring_2023&amp;rev=1704290831&amp;do=diff</link>
        <description>18-447 Course Schedule, Spring 2023

Reading assignments are to be completed BEFORE coming to class.  (P&amp;H=Computer Organization and Design RISC-V Edition: The Hardware Software Interface, 2nd Edition by Patterson and Hennessy, Morgan Kaufmann/Elsvier.) There will be additional assigned readings from research papers.</description>
    </item>
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        <dc:format>text/html</dc:format>
        <dc:date>2024-02-13T22:20:55+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>18-447_course_schedule_spring_2024</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-447_course_schedule_spring_2024&amp;rev=1707862855&amp;do=diff</link>
        <description>18-447 Course Schedule, Spring 2024

Reading assignments are to be completed BEFORE coming to class.  (P&amp;H=Computer Organization and Design RISC-V Edition: The Hardware Software Interface, 2nd Edition by Patterson and Hennessy, Morgan Kaufmann/Elsvier.) There will be additional assigned readings from research papers.</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-447_introduction_to_computer_architecture&amp;rev=1714662824&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2024-05-02T15:13:44+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>18-447_introduction_to_computer_architecture</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-447_introduction_to_computer_architecture&amp;rev=1714662824&amp;do=diff</link>
        <description>18-447 Introduction to Computer Architecture, Spring 2024

Announcements

	*  18-447 no longer has SIO scheduled lab sections.  However, TAs will host attendance-not-required “help sections” on Tuesdays 11:00am~1:50pm and Thursdays 12:30pm~3:20 in priority-reserved HH1305.</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-447_top_guns&amp;rev=1769291976&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2026-01-24T21:59:36+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>18-447_top_guns</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-447_top_guns&amp;rev=1769291976&amp;do=diff</link>
        <description>18-447 Top Guns



The best of the best each year come back to be 18-447 TAs.   In case some of you wonder who the best is, they're on this page. 

	*  2026: Scott Mionis (flight leader), Liam Carden, Soren Dupont, Feya Epel, Elisa Mayer, David Oluwafemi, Nicholas Ortiz, Vishal Setty, Kaitlyn Vitkin, Kevin Zhu,</description>
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        <dc:format>text/html</dc:format>
        <dc:date>2024-01-03T14:38:23+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>18-643_course_schedule_fall_2015</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-643_course_schedule_fall_2015&amp;rev=1704292703&amp;do=diff</link>
        <description>18-643 Course Schedule, Fall 2015 (**Not Most Recent**)

	*  Lecture notes are posted within 24 hours after the lecture
	*  Reading assignments are to be completed BEFORE coming to class.
			*  RC=Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation</description>
    </item>
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        <dc:format>text/html</dc:format>
        <dc:date>2024-01-03T14:38:02+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>18-643_course_schedule_fall_2016</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-643_course_schedule_fall_2016&amp;rev=1704292682&amp;do=diff</link>
        <description>18-643 Course Schedule, Fall 2016 (**Not Most Recent**)

	*  Lecture notes are posted within 24 hours after the lecture; you may find it useful to preview lecture notes from Fall 2015 before class. 

	*  Reading assignments are to be completed BEFORE coming to class.</description>
    </item>
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        <dc:format>text/html</dc:format>
        <dc:date>2024-01-03T14:37:37+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>18-643_course_schedule_fall_2017</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-643_course_schedule_fall_2017&amp;rev=1704292657&amp;do=diff</link>
        <description>18-643 Course Schedule, Fall 2017 (**Not Most Recent**)

	*  Lecture notes are posted within 24 hours after the lecture; you may find it useful to preview lecture notes from Fall 2016 before class. 

	*  Reading assignments are to be completed BEFORE coming to class.</description>
    </item>
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        <dc:format>text/html</dc:format>
        <dc:date>2024-01-03T14:37:15+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>18-643_course_schedule_fall_2019</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-643_course_schedule_fall_2019&amp;rev=1704292635&amp;do=diff</link>
        <description>18-643 Course Schedule, Fall 2019 (**Not Most Recent**)

	*  Lecture notes are posted within 24 hours after the lecture; you may find it useful to preview lecture notes from Fall 2017 before class. 

	*  Reading assignments are to be completed BEFORE coming to class.</description>
    </item>
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        <dc:format>text/html</dc:format>
        <dc:date>2024-01-03T14:36:48+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>18-643_course_schedule_fall_2020</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-643_course_schedule_fall_2020&amp;rev=1704292608&amp;do=diff</link>
        <description>18-643 Course Schedule, Fall 2020 (**Not Most Recent**)

	*  Lecture notes are posted within 24 hours after the lecture; you may find it useful to preview lecture notes from Fall 2019 before class. 

	*  Reading assignments are to be completed BEFORE coming to class.</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-643_course_schedule_fall_2021&amp;rev=1704292587&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2024-01-03T14:36:27+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>18-643_course_schedule_fall_2021</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-643_course_schedule_fall_2021&amp;rev=1704292587&amp;do=diff</link>
        <description>18-643 Course Schedule, Fall 2021 (**Not Most Recent**)

	*  Fall 2021 is an abbreviated 14-week semester.
	*  Lecture notes are posted within 24 hours after the lecture; you may find it useful to preview lecture notes from Fall 2020 before class. 
	*  There are 4 2-week labs in the first half of the semester. There is a single project for the second half of the semester.</description>
    </item>
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        <dc:format>text/html</dc:format>
        <dc:date>2024-01-03T14:33:32+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>18-643_course_schedule_fall_2022</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-643_course_schedule_fall_2022&amp;rev=1704292412&amp;do=diff</link>
        <description>18-643 Course Schedule, Fall 2022 (**Not Most Recent**)

	*  Fall 2022 is an abbreviated 14-week semester.
	*  Lecture notes are posted within 24 hours after the lecture; you may find it useful to preview lecture notes from Fall 2021 before class. 
	*  There are 4 2-week labs in the first half of the semester. There is a single project for the second half of the semester.</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-643_course_schedule_fall_2023&amp;rev=1704292388&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2024-01-03T14:33:08+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>18-643_course_schedule_fall_2023</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-643_course_schedule_fall_2023&amp;rev=1704292388&amp;do=diff</link>
        <description>18-643 Course Schedule, Fall 2023

	*  Lecture notes are posted within 24 hours after the lecture; you may find it useful to preview lecture notes from Fall 2022 before class. 
	*  There are 4 2-week labs in the first half of the semester. There is a single project for the second half of the semester.</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-643_course_schedule_fall_2026&amp;rev=1791119882&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2026-10-04T13:18:02+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>18-643_course_schedule_fall_2026</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-643_course_schedule_fall_2026&amp;rev=1791119882&amp;do=diff</link>
        <description>18-643 Course Schedule, Fall 2026

	*  Lecture notes are posted within 24 hours after the lecture; you may find it useful to preview lecture notes from Fall 2023 before class. 
	*  There are 4 2-week labs in the first half of the semester. There is a single project for the second half of the semester.</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-643_reconfigurable_logic&amp;rev=1790608559&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2026-09-28T15:15:59+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>18-643_reconfigurable_logic</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=18-643_reconfigurable_logic&amp;rev=1790608559&amp;do=diff</link>
        <description>18-643 Reconfigurable Logic: Technology, Architecture and Applications (Fall 2026)

You can get a good idea about this course from the 
F23 course materials (last time offered).  You can also take a closer look at the lab projects.

Announcements

	*  When the course started in 2015, “RTL” was made a required background.  If you are skilled in high-performance parallel programming, you should do fine in the current course.  (If you need an RTL refresher, go to</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=2009_memocode_co-design_contest&amp;rev=1637551351&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2021-11-22T03:22:31+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>2009_memocode_co-design_contest</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=2009_memocode_co-design_contest&amp;rev=1637551351&amp;do=diff</link>
        <description>2009 MEMOCODE HW/SW Co-Design Contest

We like to thank  IEEE Council on Electronic Design and Automation (CEDA),   Bluespec and   Xilinx for sponsoring the 2009 contest.

Final Results

The winner of this year's Absolute Performance Prize is Team TeleTitanium (Daniel L. Rosenband and Till Rosenband).  The winner of this year's Normalized Performance Prize is Team MIT (A. Agarwal, N. Dave, K. Fleming, A. Khan, M. King, M. Ng, M. Vijayaraghavan, CSAIL, MIT).  Each prize carries with it a $1000 ca…</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=a_short_intro_to_modelsim_verilog_simulator&amp;rev=1662055716&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2022-09-01T18:08:36+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>a_short_intro_to_modelsim_verilog_simulator</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=a_short_intro_to_modelsim_verilog_simulator&amp;rev=1662055716&amp;do=diff</link>
        <description>A Short Intro to ModelSim Verilog Simulator

This is a beginner's tutorial to get you off the ground from scratch. Detailed tutorials on various aspects of Modelsim can be found here: /afs/ece/support/mgc/mgc.release/modelsim-se_2020.1/modeltech/docs/pdfdocs/modelsim_se_tut.pdf</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=a_short_intro_to_synopsys_design_compiler&amp;rev=1506694282&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2017-09-29T14:11:22+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>a_short_intro_to_synopsys_design_compiler</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=a_short_intro_to_synopsys_design_compiler&amp;rev=1506694282&amp;do=diff</link>
        <description>A Short Intro to Synopsys Design Compiler (Last edited in 2009)

Synopsys Design Compiler is a software package that compiles synthesizable Verilog into a netlist to target an ASIC standard cell library. In 18-447, we will use this tool to verify that your Verilog code is, indeed, synthesizable. Design Compiler takes a special synthesis script and your synthesizable Verilog hardware description and produces a netlist and estimates for timing, power consumption, and circuit area of your circuit, …</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=a_term_project_for_teaching_superscalar_out-of-order&amp;rev=1712697631&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2024-04-09T21:20:31+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>a_term_project_for_teaching_superscalar_out-of-order</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=a_term_project_for_teaching_superscalar_out-of-order&amp;rev=1712697631&amp;do=diff</link>
        <description>A Term Project for Teaching Superscalar Out-of-Order

Hiatus starting 2024

In-person Superscalar Club is taking a break while I am on sabbatical.  I started a Piazza page to answer questions for anyone who wants to self-study. 

Revival since 2019

I am reviving this project as my extra-curricular activity.  You can follow my (very slow) work-in-progress.</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=about_pittsburgh&amp;rev=1506694282&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2017-09-29T14:11:22+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>about_pittsburgh</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=about_pittsburgh&amp;rev=1506694282&amp;do=diff</link>
        <description>About Pittsburgh

	*   Pittsburgh in Wikipedia
	*   The Official City of Pittsburgh Website
	*   The Most Liveable City in the United States
	*   Historical Weather Data and Forecasts 

	*   Pittsburg or Pittsburgh?
	*   Pittsburgh International Airport

	*  Professional Sports
		*   Steelers

		*   Penguins

		*   Pirates 



	*  Useful articles from  Pop City Magazine
		*  The Updated Guide to Downtown Pittsburgh
		*  The Hip Guide to Pittsburgh
		*  Pittsburgh Bloggers: What's New Out There
	…</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=bhsc14&amp;rev=1637551891&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2021-11-22T03:31:31+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>bhsc14</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=bhsc14&amp;rev=1637551891&amp;do=diff</link>
        <description>(Inactive Page) Does Hardware Design Have to be Hard?

Most of the materials has since made it into 18-643

BeiHang University Short Course 9/22~9/26/2014

Continued performance scaling must be accompanied by expending less energy per operation. Without Dennard scaling, mapping computation directly onto hardware—avoiding the execution overhead of software—is the most direct way to achieve the needed energy/power reduction for the most performance demanding applications. The increasingly capable …</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=cluster_computing&amp;rev=1637551407&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2021-11-22T03:23:27+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>cluster_computing</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=cluster_computing&amp;rev=1637551407&amp;do=diff</link>
        <description>Cluster Computing

Once upon a time, I developed the  StarT-X and  StarT-Jr parallel systems. In 1998, a  Hyades StarT-X Cluster with 32 400MHz Pentium-II Xeon processors was delivered to MIT's Earth Atmosphere and Planetary Science Department.  For several years, the cluster was their primary facility for running MITgcmUV (a general circulation model for climate simulation) in research and courses.</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=digital_signal_processing_hardware&amp;rev=1637551231&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2021-11-22T03:20:31+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>digital_signal_processing_hardware</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=digital_signal_processing_hardware&amp;rev=1637551231&amp;do=diff</link>
        <description>Digital Signal Processing Hardware

This research develops a domain-specific hardware synthesis framework for digital signal processing (DSP) computations.  By incorporating domain-specific knowledge of mathematics and algebra into a synthesis tool, the proposed framework can manipulate a math-level transform description to optimize a DSP transform implementation at the algorithmic and architectural design level.  This research is affiliated with the</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=fpga_architecture_for_computing&amp;rev=1675430106&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2023-02-03T13:15:06+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>fpga_architecture_for_computing</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=fpga_architecture_for_computing&amp;rev=1675430106&amp;do=diff</link>
        <description>FPGA Architecture for Computing

Field Programmable Gate Arrays (FPGAs) have been undergoing a dramatic transformation from a logic technology to a computing technology. Notwithstanding the rapid progress we have seen, there are still much untapped opportunities in FPGAs’ full computing potential. FPGAs are “programmable” devices like processors, but we have not seen FPGAs deployed, even for compute applications, with dynamism anywhere near processors.  Research is needed to fully develop and ex…</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=fpga_prototyping_and_emulation_of_computer_systems&amp;rev=1637551862&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2021-11-22T03:31:02+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>fpga_prototyping_and_emulation_of_computer_systems</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=fpga_prototyping_and_emulation_of_computer_systems&amp;rev=1637551862&amp;do=diff</link>
        <description>FPGA Prototyping and Emulation of Computer Systems

This research explores the application of Field Programmable Gate Arrays (FPGA) and High-level Hardware Synthesis technologies in computer systems prototyping and emulation.  This research has been supported in funding and/or equipment by NSF, FCRP/C2S2, SUN, and Xilinx.  Please see the</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=fpgas_for_input-dependent_irregular_stream_processing&amp;rev=1742492978&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2025-03-20T17:49:38+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>fpgas_for_input-dependent_irregular_stream_processing</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=fpgas_for_input-dependent_irregular_stream_processing&amp;rev=1742492978&amp;do=diff</link>
        <description>FPGAs for Input-Dependent, Irregular Stream Processing

 This page is under development in realtime.

This not a new effort by a convergence and continuation of key efforts.

	*  Intel/VMware Crossroads 3D-FPGA Academic Research Center  
	*  FPGA Architecture for Computing 
	*  Pigasus Network Intrusion Detection and Prevention System

The new explicit focus on developing FPGAs for Input-Dependent, Irregular Stream Processing motivated a new clean slate project page.</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=graphgen&amp;rev=1637552060&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2021-11-22T03:34:20+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>graphgen</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=graphgen&amp;rev=1637552060&amp;do=diff</link>
        <description>GraphGen: Compiling Graph Algorithms for Accelerator Platforms

This project proposes and investigates GraphGen, a domain-specific compiler that accepts graph algorithms described in a widely used vertex-centric graph specification to target a diverse range of non-Von-Neumann accelerator platforms. The goal of GraphGen is to enable application- and algorithm-level programmers without specific platform expertise to nevertheless be able to take advantage of the performance and energy efficiency of…</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=home&amp;rev=1793024765&amp;do=diff">
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        <dc:date>2026-10-26T14:26:05+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>home</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=home&amp;rev=1793024765&amp;do=diff</link>
        <description>James C. Hoe's Home Page

I am a Professor of Electrical and Computer Engineering at Carnegie Mellon University.  (My official webpage.) My research interests include computer architecture, reconfigurable computing, and high-level hardware description and synthesis. I received my PhD in EECS from MIT in 2000 (S.M., 1994). I received my BS in EECS from UC Berkeley in 1992.  I am an IEEE Fellow (2013).</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=how_to_contact_me&amp;rev=1769290944&amp;do=diff">
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        <dc:date>2026-01-24T21:42:24+00:00</dc:date>
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        <title>how_to_contact_me</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=how_to_contact_me&amp;rev=1769290944&amp;do=diff</link>
        <description>How to Contact Me

Email: jhoe+www at cmu.edu

Phone: (412) 268-4259

Mailing Address:

James C. Hoe

425 Hamerschlag Drive

Hamerschlag Hall, Room 1301

Pittsburgh, PA 15213

Physical Address:

Carnegie Mellon University

Hamerschlag Hall, ECE-HH-A304</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=memocode_2009_design_contest_faq&amp;rev=1637552218&amp;do=diff">
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        <dc:date>2021-11-22T03:36:58+00:00</dc:date>
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        <title>memocode_2009_design_contest_faq</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=memocode_2009_design_contest_faq&amp;rev=1637552218&amp;do=diff</link>
        <description>MEMOCODE 2009 Design Contest FAQ

Isn't the interpolation as defined overly simplified?

The required computation is completely contrived.  Interpolation/projection from Cartessian-to-polar (and vice versa) is much more involved in the real-world.  We purposely simplified problem to allow people to focus on the more universal design problem of managing concurrency and locality.  We don't want the</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=memocode_hw_sw_co-design_contest&amp;rev=1637552238&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2021-11-22T03:37:18+00:00</dc:date>
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        <title>memocode_hw_sw_co-design_contest</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=memocode_hw_sw_co-design_contest&amp;rev=1637552238&amp;do=diff</link>
        <description>(Inactive Page) HW/SW Co-Design Projects

I co-organized the contests below.  The contest materials are all open source (including
many of the solutions).

	*   2007 MEMOCODE HW/SW Co-Design Contest 
	*   2009 MEMOCODE HW/SW Co-Design Contest

 Contact me if you are interested in using the project materials.  

You should also Google “</description>
    </item>
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        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>operation_centric_hardware_abstraction</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=operation_centric_hardware_abstraction&amp;rev=1637552110&amp;do=diff</link>
        <description>Operation Centric Hardware Abstraction

This research investigates a high-level hardware design framework that supports a new hardware design abstraction that is fundamentally different from RTL.  This framework is based on an operation-centric abstraction for hardware description. In an operation-centric description, the behavior of a system is decomposed
and described as a collection of atomic operations.</description>
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        <dc:format>text/html</dc:format>
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        <title>pipeline_synthesis_from_transaction-based_specifications</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=pipeline_synthesis_from_transaction-based_specifications&amp;rev=1639607975&amp;do=diff</link>
        <description>Pipeline Synthesis From Transaction-based Specifications

Pipelining is a classic and widely used microarchitectural optimization to improve performance and efficiency. Pipelining a datapath by hand is tedious and error prone, as it requires the designer to reason about subtle corner cases when sequentially dependent operations are processed concurrently in different pipeline stages. Adding pipeline optimizations such as forwarding, speculation, and multithreading further exacerbates the problem…</description>
    </item>
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        <dc:format>text/html</dc:format>
        <dc:date>2021-11-22T03:35:38+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>projects_for_graduate_computer_architecture_courses</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=projects_for_graduate_computer_architecture_courses&amp;rev=1637552138&amp;do=diff</link>
        <description>(Inactive Page) Projects for Graduate Computer Architecture Courses

I developed these four projects with Kai Yu and  Eric Chung, for  CMU 18-741 Advanced Computer Architecture in Fall 2005. The projects were given out in synch with the lectures. Each project lasts 2 to 3 weeks. The emphasis is on really figuring out what is going on in these bread-and-butter topics.</description>
    </item>
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        <dc:format>text/html</dc:format>
        <dc:date>2021-11-22T03:32:02+00:00</dc:date>
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        <title>reliable_processors_and_systems</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=reliable_processors_and_systems&amp;rev=1637551922&amp;do=diff</link>
        <description>Reliable Processors and Systems

This research investigates the impact of soft-error tolerance in future deep-submicron microprocessor designs. The study investigates different options to achieve the desired level of protection against soft errors. This research effort is in part supported by NSF through a CAREER Award.   The</description>
    </item>
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        <dc:date>2026-10-26T14:27:34+00:00</dc:date>
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        <title>research</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=research&amp;rev=1793024854&amp;do=diff</link>
        <description>Research

James C. Hoe is interested in many aspects of computer architecture and digital hardware design.  His current research focuses on computer architecture, reconfigurable computing, and high-level hardware design and synthesis. 

	*  Google Scholar Profile
	*   Student theses
	*</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=smarts_simulation_sampling&amp;rev=1637551965&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2021-11-22T03:32:45+00:00</dc:date>
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        <title>smarts_simulation_sampling</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=smarts_simulation_sampling&amp;rev=1637551965&amp;do=diff</link>
        <description>SMARTS Simulation Sampling

SMARTS is a framework that applies statistical sampling to accelerate microarchitecture simulation. It employs systematic sampling to measure only a very small portion of the entire application being simulated. The accelerated simulation rate allows complete benchmarks to be used in performance studies. SMARTS is a part of</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=students&amp;rev=1792642941&amp;do=diff">
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        <dc:date>2026-10-22T04:22:21+00:00</dc:date>
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        <title>students</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=students&amp;rev=1792642941&amp;do=diff</link>
        <description>Students

Current Students

	*  Jason Cheung (started F'2022)

	*  Sanjay Seshan (started F'2025)

	*  ​Simon Yu (started F'2023)

Graduated Students

	*  Eric Tang (PhD, ECE/CMU, 12/2026) (Programming Models for Efficient Data Orchestration in Memory-Centric Systems) Co-advised with Franz Franchetti.
	*  Edwin Lim (MS, ECE/CMU, 8/2026)</description>
    </item>
    <item rdf:about="https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=teaching_history&amp;rev=1776110173&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2026-04-13T19:56:13+00:00</dc:date>
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        <title>teaching_history</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=teaching_history&amp;rev=1776110173&amp;do=diff</link>
        <description>Teaching History

	* 18-100 Introduction to Electrical and Computer Engineering
ECE Course Description
Spring 2015 Syllabus and Lecture Notes
Spring 2015, Fall 2013, Spring 2013, Fall 2012, Spring 2012, Fall 2011

	* 18-240 Structure and Design of Digital Systems
ECE Course Description
Fall 2008, Fall 2007, Fall 2006

	*  (current rotation)</description>
    </item>
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        <dc:date>2026-01-24T21:46:21+00:00</dc:date>
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        <title>teaching</title>
        <link>https://users.ece.cmu.edu/~jhoe/doku/doku.php?id=teaching&amp;rev=1769291181&amp;do=diff</link>
        <description>Teaching Related

	*  Teaching Assignments
		*  Spring: 18-447 Introduction to Computer Architecture
		*  Fall: 18-643 Reconfigurable Logic: Technology, Architecture and Applications
		*  A Term Project for Teaching Superscalar Out-of-Order
		*  Historical</description>
    </item>
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