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a_term_project_for_teaching_superscalar_out-of-order [2022/04/12 11:16] – [Revival since 2019] edita_term_project_for_teaching_superscalar_out-of-order [2023/03/20 14:27] (current) – [Revival since 2019] edit
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 I am reviving this project as my extra-curricular activity.  You can follow my (very slow) work-in-progress. I am reviving this project as my extra-curricular activity.  You can follow my (very slow) work-in-progress.
  
-So far, I developed an RTL-exact [[https://github.com/jhoecmu/ooo-beta |solution]] to the 4-inst OOO design problem.  While the datapath is modeled with exactitude with respect to the Yeager R10K paper, the solution is in the form of C++ objects. I could have coded RTL in Verilog or SystemC, but, as a learning aide, I hope many more people could read this model in C, and trace the model's "synchronous register-transfer" operation easily in a C debugger.+So far, I developed an RTL-exact [[https://github.com/jhoecmu/ooo-beta |solution]] to the 4-inst OOO design problem.  While the datapath is modeled in structure and timing with exactitude with respect to the Yeager R10K paper, the "RTL" solution is in the form of C++ objects. I could have coded RTL in Verilog or SystemC, but, as a learning aide, I hope many more people could read this model in C, and trace the model's "synchronous register-transfer" operation easily in a C debugger.
  
 I am working on a set of slides to present this topic to the serious-minded.  I am working on a set of slides to present this topic to the serious-minded.