Pipelining is a classic and widely used microarchitectural optimization to improve performance and efficiency. Pipelining a datapath by hand is tedious and error prone, as it requires the designer to reason about subtle corner cases when sequentially dependent operations are processed concurrently in different pipeline stages. Adding pipeline optimizations such as forwarding, speculation, and multithreading further exacerbates the problem. We are developing a novel transactional datapath specification (T-spec) and its accompanying synthesis technology (T-piper) to facilitate the development of in-order pipelined designs. T-spec captures an abstract datapath, whose execution semantics is interpreted as a sequence of “transactions.” Automatic T-piper analysis, based on designer-specified pipeline-stage boundaries, identifies forwarding and speculation opportunities and generates an optimized RTL-Verilog implementation that correctly and efficiently pipelines the execution of the transactions. We have applied T-spec and T-piper in design case studies on RISC (Mips) and CISC (Intel x86) processor pipeline developments. We have collaborated with Timothy Kam (SCL/Intel) and Shih-Lien Lu (MRL/Intel) on this investigation.