Don Thomas Papers

Don Thomas Papers

Updated: 12 December 1998
  1. H. Schmit and D. E. Thomas,
    "Synthesis of Application-Specific Memory Designs,"
    IEEE Transactions on VLSI Systems.
    Vol. 5, No. 1.
    March 1997.

  2. P. Sawkar and D. Thomas,
    "Partitioning for Performance for FPGAs," IEEE Transactions on CAD,
    September 1997.

  3. H. Schmit and D.E. Thomas,
    "Address Generation for Memories Containing Multiple Arrays,"
    IEEE Transactions on CAD,
    November, 1997.

  4. S. Cadambi, J. Weener, S. C. Goldstein, H. Schmit & D.E. Thomas,
    "Managing Pipeline-Reconfigurable FPGAs,"
    Sixth ACM International Symposium on Field-Programmable Gate Arrays,
    September 1998.

  5. Joe LoCicero and Donald E. Thomas,
    "A Multiheaded, Multiple Language Hardware/Software Cosimulator,"
    DAC'98,
    June 1997.

  6. D. J. Pursley, S. Coumeri and D.E. Thomas
    "The effectiveness of Transition Counting as a Predictor of Relative Energy Consumption,"
    DAC'98,
    June 1998

  7. William E. Dougherty, David J. Pursley & Donald E. Thomas,
    "Instruction Subsetting: Trading Power for Programmability,"
    1998 CODES/CASHE Workshop on Hardware/Software Codesign,
    December 1997.

  8. H. Schmit and D. E. Thomas,
    "Synthesis of Application-Specific Memory Designs,"
    IEEE Transactions on VLSI Systems.
    March 1997.

  9. H. Schmit and D. Thomas,
    "Address Generation for Memories Containing Multiple Array,"
    IEEE Transactions on CAD,
    April 1996.

  10. P. Sawkar and D. Thomas,
    "Partitioning for Performance for FPGAs,"
    IEEE Transactions on CAD, April 1996.
    Pursley, David J. and Donald E. Thomas,
    "Power consumption analysis for system level design tradeoffs," Techon '96,
    September 1996.

  11. Sari L. Coumeri and Donald E. Thomas,
    "Effects of High Level Design Decisions on Power Consumption,"
    Techon 96',
    June 1996.

  12. Jay K. Adams and D. Thomas,
    "Design of Mixed Hardware/Software Systems,
    " Proceedings of 33rd Design Automation Conference,
    pp.515-520
    June 1996,
    .
    Sari L. Coumeri, David J. Pursley, and Donald E. Thomas,
    "Power Consumption Analysis of System Level Design Trade-Offs,"
    DAC'97,
    October 1996.

  13. Donald Thomas,
    "Hardware/Software Partitioning," Hardware/Software Workshop,
    Dagstuhl, Germany,
    April 1996.

  14. D.E. Thomas and D.P. Sewerage,
    "Measuring Designer Performance to Verify Design Automation Systems,"
    Proceedings of the 14th Design Automation Conference,
    New Orleans, LA,
    June 1977.

  15. E.A. Snow, D.P. Siewiorek and D.E.Thomas,
    "A Technology-Relative Computer-Aided Design System: Abstract Representations, Transformations and Design Trade-offs,"
    Proceedings of the 15th Design Automation Conference,
    June 1978.

  16. D.E. Thomas, "A Laboratory Environment for the Introduction of Microprocessor Systems into the Electrical Engineering Curriculum: Methodology and Experiences," IEEE Transactions on Education, E-22, M
    y 1979.

  17. A.C. Parker, D.E. Thomas, D.P. Siewiorek, M. Barbacci, L. Hafer, G. Leive and J. Kim,
    "The CMU Design Automation System: An Example of Automated Data Path Design," Proceedings of the 16th Design Automation Conference,
    San Diego,
    June 1979.

  18. D.E. Thomas and D.P.Siewiorek,
    "Measuring Designer Performance to Verify Design Automation Systems,"
    IEEE Transactions on Computers,
    January 1981.

  19. D.E.Thomas,
    "An Interdisciplinary Course in Real-Time Computing,"
    IEEE Transactions on Education,
    February 1981.

  20. G.W. Leive and D.E.Thomas, "A Technology Relative Logic Synthesis and Module Selection System,"
    Proceedings of the 18th Design Automation Conference,
    June 1981.

  21. S.W. Director, A.C. Parker, D.P. Siewiorek and D.E.Thomas,
    "A Design Methodology and Computer Aids for Digital VLSI Systems,"
    IEEE Transactions on Circuits and Systems,
    Vol. 28,
    July 1981.

  22. D.E.Thomas,
    "The Automatic Synthesis of Digital Systems,"
    Proceeding of the IEEE, (invited).,
    Vol. 69, No. 10,
    pages 1200-1211.
    November 1981.

  23. J.A. Nestor and D.E. Thomas,
    "Defining and Implementing a Multilevel Design Representation With Simulation Applications,"
    Proceedings of the 19th Design Automation Conference,
    July 1982.

  24. D.E. Thomas and G. Leive,
    "Automating Technology Relative Logic Synthesis and Module Selection," IEEE Transactions on Computer Aided Design.
    Volume CAD-2, No. 2,
    pages 94-105.
    April 1983.

  25. T.J. Kowalski and D.E.Thomas,
    "The VLSI Design Automation Assistant; Prototype System,"
    Proceedings of the 20th Design Automation Conference,
    June 1983.

  26. R.A. Walker and D.E. Thomas,
    "Behavioral Level Transformation in the CMU-DA System,"
    Proceedings of the 20th Design Automation Conference,
    June 1983.

  27. C.Y. Hitchcock III and D.E. Thomas
    "A Method of Automatic Data Path Synthesis," Proceedings of the 20th Design Automation Conference,
    June 1983.

  28. J.A. Nestor and D.E. Thomas,
    "Defining and Implementing a Multilevel Design Representation With Simulation Applications,"
    IEEE Transactions on Computer Aided Design.
    Volume CAD-2, No. 3,
    pages 135-145.
    July 1983.

  29. R.L. Smith, A. Thiele, A. Das, D.E.Thomas, M.H. Kryder,
    "A Major-Minor Loop Memory Organization with Invisible Faulty Loop Correction,"
    IEEE Transactions on Magnetics,
    September 1983.

  30. T.J. Kowalski and D.E. Thomas,
    "The VLSI Design Automation Assistant: What's in a Knowledge Base," Proceedings of the 22nd IEEE Design Automation Conference.
    Las Vegas, NV.
    June 1985.

  31. J.V. Rajan and D.E. Thomas,
    "Synthesis by Delayed Binding of Decisions,"
    Proceedings of the 22nd IEEE Design Automation Conference.
    Las Vegas, NV.
    June 1985.

  32. R. Walker and D.E. Thomas
    A Model of Design Representation," Proceedings of the 22nd IEEE Design Automation Conference.
    Las Vegas, NV.
    June 1985.

  33. J.A. Nestor and D.E. Thomas,
    "Behavioral Synthesis with Interfaces,"
    International Conference on Computer Aided Design,
    Santa Clara, CA.
    November 10-13, 1986.

  34. D. E. Thomas, R. Blackburn, J.V. Rajan,
    "Linking the Behavioral and Structural Domains of Representation of Digital System Design,"
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Volume CAD-6, No. 1,
    pages 103-110.
    January 1987.

  35. R. A. Walker and D. E. Thomas,"
    Design Representation and Transformation in the System Architect's Workbench," International Conference on Computer Aided Design,
    Santa Clara, CA.
    November 9-12, 1987.

  36. David John Geiger and Donald E. Thomas,
    "Special Purpose Hardware for Algorithmic Level Simulation",
    International Conference on Computer Aided Design,
    November 9-12, 1987.

  37. D.E. Thomas, E.M. Dirkes, R.A. Walker, J.V. Rajan, J.A. Nestor, R.L. Blackburn,
    "The System Architect's Workbench,"
    Proceedings of the 25th Design Automation Conference.
    Anaheim, CA.
    June 1988.

  38. D.E. Thomas, R.L. Blackburn, P. Koenig,
    "CORAL II: Linking Behavioral to Structural Design System,"
    Proceedings of the 25th Design Automation Conference.
    Anaheim, CA.
    June, 1988.

  39. E. Dirkes Lagnese and D.E. Thomas,
    "Architectural Partitioning for System Level Design,"
    Proceedings of the 26th Design Automation Conference. Las Vegas, NV.
    June 1989.

  40. R. A. Walker and D.E. Thomas,
    "Behavioral Transformation for Algorithmic Level IC Design,"
    IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems.
    Volume 8, No. 10,
    pages 1115-1128.
    October 1989.

  41. Richard J. Cloutier and Donald E. Thomas,
    "The Combination of Scheduling, Allocation, and Mapping in a Single Algorithm,"
    Proceedings of the 27th Design Automation Conference.
    Orlando, FL.
    June 1990.

  42. D.L. Springer and D.E. Thomas,
    "Exploiting the Special Structure of Conflict and Compatibility Graphs in High-Level Synthesis,"
    International Conference on Computer Aided Design. Santa Clara, CA.
    November 1990.

  43. Elizabeth D. Lagnese and Donald E. Thomas,
    "Architectural Partitioning for System Level Synthesis of Integrated Circuits,"
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Volume 10, No. 7,
    pages 847-860.
    July, 1991.

  44. D. Springer and D.E. Thomas,
    "New Methods for Coloring and Clique Partitioning in Data Path Allocation," Integration,
    The VLSI Journal,
    Vol. 12,
    pp.267-292
    1991

  45. A.J. Gadient and D.E. Thomas "
    A Dynamic Approach to Controlling High-Level Synthesis CAD Tools," Transactions on VLSI Systems,
    September 1993,
    Vol. 1, No. 3,
    pp. 328 - 341.

  46. D. Springer and Donald E. Thomas,
    "Exploiting the Special Structure of Conflict and Compatibility Graphs in High-level Synthesis,"
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.13, No. 7,
    July 1994.

  47. H. Schmit and D. E. Thomas,
    "Synthesis of Application-Specific Memory Designs,"
    IEEE Transactions on VLSI Systems, Vol. 5, No. 1.
    March 1997.

  48. P. Sawkar and D. Thomas,
    "Partitioning for Performance for FPGAs,"
    to IEEE Transactions on CAD,
    September 1997.

  49. Herman Schmit and Donald E. Thomas,
    "Address Generation for Memories Containing Multiple Arrays,"
    IEEE Transactions on CAD,
    November 1997.