Viterbi Detector

Name : Srinath Sridharan

The project that I am working on involves the design of a Viterbi detector for application in magnetic record channels. A new architecture for the implementation of the Viterbi algorithm is used. The important specs on this project are the speed at which the detector can operate and the power consumption. The goal that is being targeted at are clock speeds of about 500Mhz with a power threshold of 250mW. Power becomes crucial for this application as a cheaper form of packaging can be used retaining the low cost of the chip. As far as speed is concerned, the faster the better.

Implementation details :

The traditional bottleneck in the Viterbi algorithm has been the recursive Add-Compare-Select(ACS) loop. The Viterbi detectors that are used for Modems and RF communication purposes have there branch metrics computation within this loop as it is not feasible ( in terms of hardware requirements) for this to be done outside the loop. For use in magnetics record channels its identified that the branch metric computations can be done outside the inner loop bringing in the possibility of pipelining in this unit. Thus the three blocks that areto be used are : Branch metric computation unit, the second block for the ACS recursion and a third block for the decoding of the bits. Presently we are also investigating possible architectures that can be used for implementation of the second block.