FIR Filter for Equalization in Magnetic Channels

Name: Bharath Ramasubramanian

Bharath's research focuses on the circuits end of designing of Low power High speed FIR filters for future Magnetic Read Channels. FIR filters running at 300MHz on less than 400mw of power are being aimed at. FIR filter design at the ciruit level basically involves the design o f high speed adders and Multipliers. One way to attain this speed is to heavily pipeline the design. But this possibility is precluded by the group delay requirements of an FIR filter. So dynamic circuit approaches (not unlike Domino CMOS) are being explored to get to the targetted speed. Some tinkering is also being with multiplier architectures as a part of this endevour to crank up the speed at minimal power cost.