Signal Processing and Circuit Design for Magnetic Recording Channels

Investigators: Joshua C. Park and Prof. L. Richard Carley

Research Focus:

Continuous-Time Equalization in Magnetic Recording Channel

High-Speed Mixed-Mode Circuit Design for Signal Processing

System level study of Magnetic Recording Channels

With increasing recording densities, the signal processing requirements in the storage read channel continues to challenge the engineers. As the industry is moving toward more complex and more effective sequence detection architectures, the equalization of the channel becomes more involved and strongly dependent upon the particular detection method employed. Recently the continuous-time equalization has been gaining supports thanks to its advantages over traditional discrete-time FIR equalization despite the more elaborate design process: (1) the timing recovery loop does not include the equalizer delay, (2) the use of continuous-time analog filters and the absence of the anti-aliasing filters in the system makes it much more power-efficient.

In recent years our study has focused on the analog graphic equalizer structure for use in the EPR4+MLSD system and FDTS/DF system. This architecture was motivated by the fact that the graphic equalizer structure allows pole tuning as well as the zero adaptation. Using our in-house system-level simulator we were able to optimize the performance of our equalizer better than the typical 10-tap FIR equalizer followed by the 4th-order LPF boost. A prototype chip of our CGE (Complex Graphic Equalizer) has been fabricated which showed the data rate in excess of 200 MSymbols/sec. Currently we are working on further optimization of our CGE structure and the next generation prototype chip which should achieve the date rate in excess of 300MSymbols/sec using all CMOS digital process.