Stack Computers: the new wave © Copyright 1989, Philip Koopman, All Rights Reserved.

Chapter 5
Architecture of 32-bit Systems

32-Bit stack computers are only beginning to come into production in 1989, but will soon play a central role in the future of stack machines. In Section 5.1 we shall discuss some of the strengths and problems associated with 32-bit stack processors.

In Section 5.2, we shall discuss the Johns Hopkins University/Applied Physics Laboratory FRISC 3 design, which is also known as the Silicon Composers SC32. The FRISC 3 is a hardwired stack processor designed in the spirit of the NC4016 and its successors, but with more flexibility. It uses fairly small on-chip stack buffers that are managed by automatic buffer control circuitry.

In Section 5.3, we shall discuss the Harris RTX 32P design. The RTX 32P is a microcoded processor that is a descendent of the WISC CPU/16. It is a two-chip implementation of the WISC CPU/32 processor. The RTX 32P uses RAM-based microprogram memory to achieve flexibility. It also has rather large on-chip stack buffers. The RTX 32P is a prototype processor for a commercial 32-bit stack processor under development.

In Section 5.4, we shall discuss the Wright State University SF1 design. The SF1 is actually an ML1 stack machine which uses stack frames in multiple hardware stacks for support of C and other conventional languages. However, the SF1 has strong ML0 roots, so it forms an interesting example of how an ML1 design "stacks up" against ML0 designs.

While the implementation strategies of these three processors are quite different, all accomplish the goal of very high speed execution of stack programs.

• 5.1 WHY 32-BIT SYSTEMS?
• 5.2 ARCHITECTURE OF THE FRISC 3 (SC32)
  • 5.2.1 Introduction
  • 5.2.2 Block diagram
  • 5.2.3 Instruction set summary
  • 5.2.4 Architectural features
  • 5.2.5 Implementation and featured application areas
• 5.3 ARCHITECTURE OF THE RTX 32P
  • 5.3.1 Introduction
  • 5.3.2 Block diagram
  • 5.3.3 Instruction set summary
  • 5.3.4 Architectural features
  • 5.3.5 Implementation and featured application areas
• 5.4 ARCHITECTURE OF THE SF1
  • 5.4.1 Introduction
  • 5.4.2 Block diagram
  • 5.4.3 Instruction set summary
  • 5.4.4 Architectural features
  • 5.4.5 Implementation and featured application areas

NEXT SECTION

Phil Koopman -- koopman@cmu.edu