1. United States Patent No. 4,541,114, R. A. Rutenbar and R. M. Lougheed, “Routing techniques using serial neighborhood image analyzing system,” September 10, 1985.
  2. United States Patent No. 5,825,660, J. Cagan, A. Kolli, S. Szykman and R. A. Rutenbar, “Method of Optimizing Component Layout Using A Hierarchical Series of Models,” October 20, 1998.
  3. United States Patent No. 6,711,725, E. Fallon, R. A. Rutenbar and D. Reaves, “Method of Creating Conformal Outlines for Use in Transistor Level Semiconductor Layouts,” December, 2003.
  4. United States Patent No. 6,874,133, P. Gopalakrishnan, R. Rutenbar, E. Fallon, “Integrated circuit design layout compaction method,” March 29, 2005
  5. United States Patent No. 6,918,102, R. Rutenbar, R. Colwell, E. Fallon, “Method and apparatus for exact relative positioning of devices in a semiconductor circuit layout,” July 12, 2005.
  6. United States Patent No. 6,957,400, H. Liu, R. Phelps, R. Rutenbar, “Method and apparatus for quantifying tradeoffs for multiple competing goals in circuit design,” October 18, 2005.
  7. United States Patent No. 7,058,916, R. Phelps, R. A. Rohrer, A.J. Gadient, R. A. Rutenbar, L. R. Carley, “Method for automatically sizing and biasing circuits,” June 6, 2006.
  8. United States Patent No.7,093,220, E. Fallon, R. A. Rutenbar, “Method for generating constrained component placement for integrated circuits and packages,” August 15, 2006.
  9. United Stated Patent Application 2006020629. R. Rutenbar, J.D. Ma, C.F. Fang, A. Singhee, “Method and system for modeling uncertainties in integrated circuits, systems, and fabrication processes,” filed Sept. 14 2006.