- M. Jereminov, D. Bromberg, X. Li, G. Hug and L. Pileggi, “Improving Robustness and Modeling Generality for Power Flow Analysis” IEEE PES Transmission and Distribution Conference, Dallas, Texas, May 2016.
- M. Jereminov, D. Bromberg, A. Pandey, G. Hug, X. Li and L. Pileggi, “An Equivalent Circuit Formulation for Three-Phase Power Flow Analysis of Distribution Systems” IEEE PES Transmission and Distribution Conference, Dallas, Texas, May 2016.
- Q. Guo, T.-M. Low, N. Alachiotis, B. Akin, L. Pileggi, J.C. Hoe, F. Franchetti, Enabling Portable Energy Efficiency with Memory Accelerated Library, 48th Annual IEEE/ACM International Symposium on Microarchitecture, 2015.
- F. Wang, S. Yin, M. Jun, X. Li, T. Mukherjee, R. Negi, L. Pileggi, Re-thinking Polynomial Optimization: Efficient Programming of Reconfigurable Radio Frequency (RF) Systems by Convexification, Asia and South Pacific Design Automation Conference, January 2016.
- X. Chen, D. Bromberg, G. Hug, X. Li and L. Pileggi, ” A Robust and Efficient Power Series Method for Tracing PV Curves,” The 47th North American Power Symposium, October 2015.
- T. C. Jackson, A. A. Sharma, R. Shi, J. Weldon, and L. Pileggi, “Using TMO-based RRAM Multi-Level Cells and Nano-Oscillators for Efficient ONN Implementation,” TECHCON 2015, Austin, Texas.
- A. Sharma, T. Jackson, J. Bain, L. Pileggi and J. Weldon, “High Performance, Integrated 1T1R Oxide-based Oscillator: Stack Engineering for Low-Power Operation in Neural Network Applications,” in IEEE Symp. VLSI Technology, June 2015.
- H.E. Sumbul, K. Vaidyanathan, Q. Zhu, F. Franchetti, L. Pileggi, “Application-Specific Synthesis of Embedded Logic-in-Memory Designs”, manuscript accepted for publishing in Design Automation Conference (DAC 2015), June 2015.
- E. Calayir, J. Xu, A. Patterson, G. K. Fedder, G. Piazza, L. Pileggi, “3D Integration of AlN MEMS Filters and CMOS for Self-Healing RF Front-Ends,” Government Microcircuit Applications and Critical Technology Conference, March 2015.
- D. Bromberg, G. Hug, X. Li and L. Pileggi, “An Equivalent Circuit Formulation of the Power Flow Problem with Current and Voltage State Variables,” Powertech Eindhoven, June 2015.
- T. C. Jackson, A. A. Sharma, J. A. Bain, J. A. Weldon, and L. Pileggi, “An RRAM-Based Oscillatory Neural Network,” in Proc. 2015 Latin American Symposium on Circuits and Systems. Montevideo, Uruguay, 2015.
- Q. Guo, N. Alachiotis, B. Akin, F. Sadi, G. Xu, T.M. Low, L. Pileggi, J.C. Hoe, and F. Franchetti, “3D-Stacked Memory-Side Acceleration: Accelerator and System Design,” WoNDP: 2nd Int’l Workshop on Near-Data Processing, December 2014.
- V. Calayir, M.Darwish, J. Weldon and L. Pileggi, Analog Neuromorphic Computing Enabled by Multi-Gate Programmable Resistive Devices, Design and Test in Europe (DATE), March 2015.
- Y.-C. Wang, S. Yin, M. Jun, X. Li, L. Pileggi, T. Mukherjee, R. Negi, “Accurate Passivity-Enforced Macromodeling for RF Circuits via Iterative Zero/Pole Update Based on Measurement Data,” 20th Asia and South Pacific Design Automation Conference (ASP-DAC), 2015.
- M. Jun, R. Negi, Y.-C. Wang, T. Mukherjee, X. Li, J. Tao, and L. Pileggi, “Joint Invariant Estimation of RF impairments for Reconfigurable Radio Frequency(RF) Front-end,” Globecom Workshop – Emerging Technologies for 5G Wireless Cellular Networks, 2014.
- D. Bromberg, M. Moneck, V. Sokalski, L. Pileggi, J-G. Zhu, Experimental Demonstration of Four-Terminal Magnetic Logic Device with Separate Read- and Write-Paths, International Electron Devices Meeting, December 2014.
- D.M. Bromberg, E. Sumbul, J-G. Zhu and L. Pileggi, All-Magnetic MRAM Based on Four Terminal mCell Device, 13th Joint MMM/Intermag Conference, November 2014.
- Minhee Jun, Jun Tao, Ying-Chih Wang, Shihui Yin, Rohit Negi, Xin Li, Tamal Mukherjee and Lawrence Pileggi, “Environment-adaptable efficient optimization for programming of reconfigurable radio frequency (RF) receivers,” IEEE Military Communications Conference (MILCOM), 2014.
- F. Sadi, B. Akin, D. Popovici, J. Hoe, L. Pileggi, F. Franchetti, Algorithm/Hardware Co-optimized SAR Image Reconstruction with 3D-stacked Logic in Memory, Eighteenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory, September 2014.
- R. Liu, L. Pileggi and J. Weldon, A Wideband RF Receiver with >80 dB Harmonic Rejection Ratio, Int’l Custom Integrated Circuits Conference, September 2014.
- K. Vaidyanathan, L. Liebmann, A. Strojwas, L. Pileggi, Sub-20 nm Design Technology Co-Optimization for Standard Cell Logic, Int’l Conference on Computer-Aided Design, November 2014.
- T. Jackson, V. Calayir and L. Pileggi, Integrating Emerging Devices and CMOS for Efficient Cellular Neural Networks, Proceedings of the SRC Techcon Conference, September 2014.
- K. Vaidyanathan, R. Liu, E. Sumbul, Q. Zhu, F. Franchetti, L. Pileggi, “Efficient and Secure Intellectual Property (IP) Design with Split Fabrication”, Hardware-Oriented Security and Trust, May 2014.
- K. Vaidyanathan, B. P. Das, E. Sumbul, R. Liu, L. Pileggi, “Building Trusted ICs using Split Fabrication”, Hardware-Oriented Security and Trust, May 2014.
- K. Vaidyanathan, B. Prasad Das, L. Pileggi, “Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack,” IEEE/ACM Design Automation Conference, June 2014.
- M. T. Moneck, V. Sokalski, D. M. Bromberg, J. Wu, Z. Dai, L. Pileggi, J.-G. Zhu, “Fabrication Challenges in Developing All-Metal Magnetic Logic Circuits,” 2014 International Magnetics Conference.
- J.-G. Zhu, D. Bromberg, V. Sokalski, M.T. Moneck, J. Wu, Z. Dai, L. Pileggi, “mLogic: All Spin Logic Device and Circuits for Future Electronics,” IEEE Transactions on Magnetics, INTERMAG 2014.
- V. H-C. Chen and L. Pileggi, “A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI,” International Solid State Circuits Conference (ISSCC), February 2014.
- J. Tao, Y.-C. Wang, M. Jun, X. Li, R. Negi, T. Mukherjee, L. Pileggi, “Toward Efficient Programming of Reconfigurable Radio Frequency (RF) Receivers,” 19th Asia and South Pacific Design Automation Conference (ASP-DAC), January 2014.
- Qiuling Zhu, Berkin Akin, H. Ekin Sumbul, James C. Hoe, Larry Pileggi, Franz Franchetti, “A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing”, IEEE International 3D Systems Integration Conference, October 2-4, 2013.
- S. Sun, F. Wang, S. Yaldiz, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, J. Plouchart, B. Sadhu, B. Parker, A. Valdes-Garcia, M. Sanduleanu, J. Tierno, D. Friedman, Indirect Performance Sensing for On-Chip Analog Self-Healing via Bayesian Model Fusion, Int’l Custom Integrated Circuits Conference, September 2013.
- Qiuling Zhu, Tobias Graf, H. Ekin Sumbul, Larry Pileggi, Franz Franchetti, A Logic-in-Memory Accelerated 3D-DRAM for Sparse Matrix-Matrix Multiplication, Seventeenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory (Best Paper Award), September 2013.
- V. Calayir and L. Pileggi, All-Magnetic Analog Associative Memory, International NEWCAS Conference, June 2013.
- V. Calayir, T. Jackson, A. Tazzoli, G. Piazza and L. Pileggi, Neurocomputing and Associative Memories Based on Ovenized Aluminum Nitride Resonators, International Joint Conference on Neural Networks, August 2013.
- V. Calayir and L. Pileggi, Fully-Digital Oscillatory Associative Memories Enabled by Non-volatile Logic, International Joint Conference on Neural Networks, August 2013.
- V. H.-C. Chen and L. Pileggi, “An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI”, in IEEE Symp. VLSI Circuits, June 2013.
- J. Tao, Y-C. Wang, M. Jun, X. Li, R. Negi, T. Mukherjee and L. Pileggi, Efficient System-Level Performance Modeling and Optimization for Reprogrammable Radio Frequency (RF) Systems, Frontiers in Analog CAD Workshop, February 2013.
- E. Sumbul, A. Patterson, G. Fedder, F. Franchetti, G. Piazza and L. Pileggi, Trusted Split-Fabrication System-on-Chip Design Technology and Methodology,
*(Invited Paper)*GOMACTech Technical Program, March 2013. - K. Vaidyanathan, L. Liebmann and L. Pileggi, Rethinking ASIC design with next-generation lithography and process integration, SPIE Advanced Lithography Conference, February 2013.
- V. Sokalski, D.M. Bromberg, D. Morris, M.T. Moneck, E. Yang, L. Pileggi, J-G. Zhu, Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic, 12th Joint MMM/Intermag Conference, January 2013.
- D. Bromberg, D. Morris, L. Pileggi and J. Zhu, All-Magnetic, Nonvolatile, Addressable Chainlink Memory, 12th Joint MMM/Intermag Conference, January 2013.
- Q. Zhu, L. Pileggi and F. Franchetti, Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography, Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 2012.
- J.-O. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakani, S. Yaldiz, L. Pileggi, R. Harjani, S. Reynolds, J. A. Tierno, D. Friedman, A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS, Int’l Custom Integrated Circuits Conference, Sept. 2012.
- Q. Zhu, L. Pileggi and F. Franchetti, Smart Memory Synthesis for Energy-Efficient Computed Tomography Reconstruction, Proceedings of the SRC Techcon Conference, September 2012.
- Q. Zhu, K. Vaidyanathan, O. Shacham, M. Horowitz, L. Pileggi and F. Franchetti, Design Automation Framework for Application-Specific Logic-in-Memory Blocks, IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2012.
- B. Sadhu, M.A. Ferriss, J-O. Plouchart, A.S. Natarajan, A.V. Rylyakov, A. Valdes-Garcia, B.D. Parker, S. Reynolds, A. Babakhani, S. Yaldiz, L. Pileggi, R. Harjani, J. Tierno and D. Friedman, A 21.8-27.5GHz PLL in 32nm SOI Using Gm Linearization to Achieve -130dBc/Hz Phase Noise at 10MHz Offset from a 22GHz Carrier, 2012 Radio Frequency Integrated Circuits Symposium, June 17-19.
- D. Morris, D. Bromberg, J. Zhu and L. Pileggi, Magnetic Logic Circuits with Minimal Connections to CMOS, IEEE CAS-FEST, 2012.
- D. Morris, D. Bromberg, J. Zhu and L. Pileggi, mLogic: Ultra-Low Voltage Non-Volatile Logic Circuits Using STT-MTJ Devices, IEEE/ACM Design Automation Conference (DAC), 2012.
- D. Morris, D. Bromberg, J. Zhu, and L. Pileggi, Spintronic Circuits and Devices for Low-Voltage Electronics, (Invited Paper) In Proceedings of WOFE, 2011.
- Q. Zhu, L. Pileggi , F. Franchetti, “Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography,” VLSI-SoC, October 2012.
- F. Wang, G. Keskin, A. Phelps, J. Rotner, X. Li, G. Fedder, T. Mukherjee and L. Pileggi, “Statistical Design and Optimization for Adaptive Post-Silicon Tuning of MEMS Filters,” IEEE/ACM Design Automation Conference (DAC), 2012.
- D. Bromberg, D. Morris, L. Pileggi and J. Zhu, Novel STT-MTJ device enabling all-metallic logic circuits, International Magnetics Conference, May 2012.
- K. Vaidyanathan, S.H. NG, D. Morris, N. Lafferty, L. Liebmann, W. Huang, K. Lai, L. Pileggi, A.J. Strojwas, Design and Manufacturability Tradeoffs in Unidirectional & Bidirectional Standard Cell Images in 14 nm, SPIE Advanced Lithography Conference, February 2012.
- W. Huang, D. Morris, N. Lafferty, L. Liebmann, K. Vaidyanathan, K. Lai, L. Pileggi, A.J. Strojwas, Local Loops for Robust Inter-Layer Routing at Sub-20 nm Nodes, SPIE Advanced Lithography Conference, February 2012.
- L. Pileggi, Center for Circuit and System Solutions (C2S2): Accomplishments and Future Challenges, (Invited Paper) GOMACTech Technical Program, March 2012.
- Q. Zhu, C.R. Berger, E. Turner, L. Pileggi, F. Franchetti, Polar Format Synthetic Aperture RADAR in Energy Efficient Application-Specific Logic-in-Memory, IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto Japan, March 2012.
- D. Morris, D. Bromberg, J. Zhu, and L. Pileggi, mLogic: Ultra-Low Voltage Logic Circuits with Non-Volatile Spintronic Devices, (Invited Paper) Workshop on Frontier Electronics, December 2011.
- J. Zhu, D. Bromberg, D. Morris and L. Pileggi, Novel STT Device Design To Enable All Metallic Spin Logic Circuits Free of Transistors, (Invited Presentation) Conference on Magnetism and Magnetic Materials, October 2011.
- M. Althoff, A. Rajhans, B. Krogh, S. Yaldiz, X. Li and L. Pileggi, Formal Verification of Phase-Locked Loops Using Reachability Analysis and Continuization, Int’l Conference on Computer-Aided Design (Best Paper Award), November 2011.
- Qiuling Zhu, Franz Franchetti and Larry Pileggi, Application-Specific Logic-in-Memory for Polar Format Synthetic Aperture Radar, Fifteenth Annual High Performance Embedded Computing (HPEC) Workshop at MIT Lincoln Laboratory, September 2011.
- S. Yaldiz, V. Calayir, X. Li, L. Pileggi, et al, Indirect Phase Noise Sensing for Self-Healing Voltage Controlled Oscillators, Int’l Custom Integrated Circuits Conference, Sept. 2011.
- C.-Y. Wen, J. Paramesh, L. T. Pileggi, J. Li, S. Kim, J. Proesel, C. Lam, Post-Silicon Calibration of Analog CMOS Using Phase-Change Memory Cells, European Solid-State Device Research Conference (ESSDERC), September 2011.
- M. Althoff, A. Rajhans, B.H. Krogh, S. Yaldiz, X. Li, L. Pileggi, Using Continuization in Reachability Analysis for the Verification of a Phase-Locked Loop, In Proc. Frontiers in Analog Circuit (FAC) Synthesis and Verification, July 2011.
- D. Morris, K. Vaidyanathan and L. Pileggi, Design Without Rules: A Pattern Construct Methodology, Proceedings of the SRC Techcon Conference, September 2011.
- D. Morris, K. Vaidyanathan, N. Lafferty, K. Lai, L. Liebmann, L. Pileggi, Design of Embedded Memory and Logic Based On Pattern Constructs, IEEE Symposium on VLSI (Invited Presentation), June 2011.
- C.-Y. Wen, J. Li, S. Kim, M. Breitwisch, C. Lam, J. Paramesh, L. T. Pileggi, A Non-volatile Look-Up Table Design Using PCM (Phase-Change Memory) Cells, IEEE Symposium on VLSI, June 2011.
- S. Yaldiz, F. Wang, X. Li, L. Pileggi, A.S. Natarajan, M.A. Ferriss, J. Tierno, Virtual Phase Noise Sensor for Self-Healing Voltage Controlled Oscillators, GOMACTech-11 Technical Program, March 2011.
- V. Rovner, T. Jhaveri, Daniel Morris, Andrzej J. Strojwas, and Larry Pileggi, Performance and Manufacturability Trade-offs of Pattern Minimization for sub-22nm Technology Nodes, SPIE Advanced Lithography Conference, February 2011.
- C.-Y. Wen, E. K. Chua, R. Zhao, T. C. Chong, J. A. Bain, T. E. Schlesinger, L. T. Pileggi, J. Paramesh, A Phase-change via-Reconfigurable On-Chip Inductor, International Electron Devices Meeting, December 2010.
- G. Keskin, J. Proesel and L. Pileggi, Statistical Modeling and Post Manufacturing Configuration for Scaled Analog CMOS, Int’l Custom Integrated Circuits Conference, Sept. 2010.
- J. Proesel, G. Keskin, J.O. Plouchart and L. Pileggi, An 8-bit 1.5GS/s Flash ADC Using Post-Manufacturing Statistical Selection, Int’l Custom Integrated Circuits Conference, Sept. 2010.
- A. Bonnoit, S. Herbert and L. Pileggi, Reducing Variability in Chip-Multiprocessors with Adaptive Body Biasing, International Symposium on Low Power Electronics and Design, August 2010.
- G. Keskin, J. Proesel and L. Pileggi, Modeling of Statistical Element Selection Based Self-Healing Analog Circuits, Proceedings of the SRC Techcon Conference, September 2010.
- D. Morris, S. Rovner, L. Pileggi, A. Strojwas and K. Vaidyanathan, Enabling Application-Specific Integrated Circuits on Limited Pattern Constructs, IEEE Symposium on VLSI (Invited Presentation), June 2010.
- L. Liebmann, J. Hibbeler, N. Hieter, L. Pileggi, M. Moe, T. Jhaveri, V. Rovner, Demonstrating the benefits of template-based design-technology co-optimization, SPIE Advanced Lithography Conference, February 2010.
- T. Jhaveri, U. Urslan, V. Rovner, L. Pileggi & A. J. Strojwas, Application of the Cost-Per-Good-Die Metric for Process-Design Co-optimization, SPIE Advanced Lithography Conference, Selected for Keynote Presentation, February 2010.
- A. Bonnoit, S. Herbert, L. Pileggi and D. Marculescu, Integrating Dynamic Voltage/Frequency Scaling and Adaptive Body Biasing using Test-time Voltage Selection, International Symposium on Low Power Electronics and Design, August 2009.
- J. Proesel, G. Keskin and L. Pileggi, An 8-bit Flash ADC using Statistical Element Selection, Proceedings of the SRC Techcon Conference, September 2009.
- U. Arslan, J. Wang and L. Pileggi, An SRAM Design Framework for Deeply-Scaled CMOS, Proceedings of the SRC Techcon Conference, September 2009.
- B. Taylor, D. Morris and L. Pileggi, Fixed Depth Reasoning in Satisfiability and its Applications to Combinatorial Optimization, Proceedings of the SRC Techcon Conference, September 2009.
- T. Jhaveri, A. J. Strojwas, L. Pileggi and V. Rovner, Economic Assessment of Lithography Strategies for the 22nm Technology Node, Proceedings of the SPIE/BACUS Symposium on Photomask Technology, September 2009.
- A. J. Strojwas, T. Jhaveri, V. Rovner and L. Pileggi, Creating an Affordable 22nm Node using Design-Lithography Co-Optimization, Proceedings of ACM/IEEE Design Automation Conference, June 2009.
- J. Wang, S. Yaldiz, X. Li and L. Pileggi, SRAM Parametric Failure Analysis, Proceedings of ACM/IEEE Design Automation Conference, June 2009.
- S. Yaldiz, U. Arslan, X. Li and L. Pileggi, Efficient Statistical Analysis of Read Timing Failures in SRAM Circuits, IEEE Int’l Symposium on Quality in Electronic Design, March 2009.
- Lars Liebmann, Larry Pileggi, Jason Hibbeler, Vyacheslav Rovner, Tejas Jhaveri, Greg Northrop, Simplify to Survive: Prescriptive Layouts Ensure Profitable Scaling to 32nm and Beyond, SPIE Advanced Lithography Conference, February 2009.
- Tejas Jhaveri, Andrzej Strojwas, Larry Pileggi & Vyacheslav Rovner, OPC Simplification & Mask Cost Reduction using Regular Design Fabrics, SPIE Advanced Lithography Conference, February 2009.
- Bin Wan, Jian Wang, Gokce Keskin, and Lawrence T. Pileggi, Ring Oscillators for Single Process-Parameter Monitoring, IEEE Workshop on Test Structure Design for Variability Characterization, November 2008.
- J. Proesel and L. Pileggi, A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS, Int’l Custom Integrated Circuits Conference, Sept. 2008.
- U. Arslan, M. McCartney, M. Bhargava, X. Li, K. Mai and L. Pileggi, Variation-Tolerant SRAM Sense-Amplifier Timing Using Configurable Replica Bitlines, Int’l Custom Integrated Circuits Conference, Sept. 2008.
- L. Pileggi, G. Keskin, X. Li, K. Mai and J. Proesel, Mismatch Analysis and Statistical Design at 65 nm and Below, Invited Paper, Int’l Custom Integrated Circuits Conference, Sept. 2008.
- U. Arslan, M. McCartney, M. Bhargava, L. Pileggi and K. Mai, Variation-Tolerant SRAM Sense-Amp Timing using Configurable Replica Bitlines, Proceedings of the SRC Techcon Conference, September 2008.
- J. Proesel and L. Pileggi, A 0.6-to-1V Inverter-Based 5-bit Flash ADC in 90nm Digital CMOS, Proceedings of the SRC Techcon Conference, September 2008.
- G. Keskin, L. Pileggi, X. Li and K. Mai, Process Variation Effects on Input Offset Voltage of CMOS SRAM Sense Amplifiers, Proceedings of the SRC Techcon Conference, September 2008.
- E. Small, S.M. Sadeghipour, L. Pileggi, M. Asheghi, Thermal Analyses of Confined Cell Design for Phase Change Random Access Memory (PCRAM), ITherm, May 2008.
- T. Jhaveri, A.J. Strojwas, L. Pileggi, V. Rovner, Enabling Technology Scaling with “In Production” Lithography Processes, SPIE Advanced Lithography Conference, February 2008.
- J. Brown, B. Taylor, R. D. Blanton, and L. Pileggi, Automated Testability Enhancements for Logic Brick Libraries, Proceedings of Design and Test Europe, March 2008.
- B. Taylor and L. Pileggi, Exact Methods for Physical Design of Regular Logic Bricks, Proceedings of the SRC Techcon Conference, October 2007.
- X. Li, B. Taylor, Y-T. Chen and L. Pileggi, Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization , Proceedings of the International Conference on Computer-Aided Design, November 2007.
- K. Yu, S. Wang, A. Gerdemann, C. Weldon, D. Reber, J. Vasek, S. Veeraraghavan, V. Rovner, T. Jhaveri, T. Hersan, L. Pileggi, Regular Layout Performance Dependence on Cell Abutment, Joint Conference on Design For Manufacturing, June 20-22, 2007.
- J. Wang, X. Li and L. Pileggi, Parameterized Macromodeling for Analog System-Level Design Exploration, Proceedings of ACM/IEEE Design Automation Conference, June 2007.
- B.Taylor and L. Pileggi, Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks, Proceedings of ACM/IEEE Design Automation Conference, June 2007.
- X. Li and L. Pileggi, Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits, Proceedings of ACM/IEEE Design Automation Conference, June 2007.
- K.Y. Tong, V. Rovner and L. Pileggi, Synthesis of Regular Logic Bricks for Robust IC Design, Int’l Conference on Computer Design, October 2006.
- G. Keskin, X. Li and L. Pileggi, Active On-Die Suppression of Power Supply Noise, Int’l Custom Integrated Circuits Conference, Sept. 2006.
- P. Gopalakrishnan, X. Li and L. Pileggi, A Metric-Embedding Inspired Approach to Timing-driven FPGA Placement, Design Automation Conference, June 2006.
- X. Li, J. Le and L. Pileggi, Projection-Based Statistical Analysis of Full-Chip Leakage Power with Non-Log-Normal Distributions, Design Automation Conference, June 2006.
- T. Jhaveri, L. Pileggi, V. Rovner, A.J. Strojwas, Maximization of layout printability/manufacturability by extreme layout regularity, SPIE 31st International Symposium on Microlithography Symposium (invited presentation), February 2006.
- L. Pileggi and A.J. Strojwas, Regular Fabrics for Nano-Scaled CMOS Technologies, International Solid State Circuits Conference (invited presentation), February 2006.
- X. Li, J. Le, L. Pileggi and A.J. Strojwas, Projection-Based Performance Modeling for Inter/Intra-Die Variations, Proceedings of the International Conference on Computer-Aided Design, November 2005.
- X. Li, J. Le, M. Celik and L. Pileggi, Defining Statistical Sensitivity for Timing Optimization of Logic Circuits with Large-Scale Process and Environmental Variations, Proceedings of the International Conference on Computer-Aided Design, November 2005.
- X. Li, P. Li and L. Pileggi, Parameterized Interconnect Order Reduction with Explicit-and-Implicit Multi-Parameter Moment Matching for Inter/Intra-Die Variations, Proceedings of the International Conference on Computer-Aided Design, November 2005.
- X. Li, J. Wang, W. Chiang and L. Pileggi, Performance-Centering Optimization for System-Level Analog Design Exploration, Proceedings of the International Conference on Computer-Aided Design, November 2005.
- P. Li, Y. Dong and L. Pileggi, Temperature-Dependent Optimization of Cache Leakage Power Dissipation, Proceedings of the International Conference on Computer Design, October 2005.
- R. Batra, P. Li, L. Pileggi, W.J. Chiang, A Behavioral Level Approach for Nonlinear Dynamic Modeling of Voltage-Controlled Oscillators, Int’l Custom Integrated Circuits Conference, Sept. 2005.
- G. Keskin, X. Li and L. Pileggi, Reducing Power Supply Noise in Integrated Circuits Using Active Resistors, Proceedings of the SRC Techcon Conference, October 2005.
- P. Gopalakrishnan and L. Pileggi, Timing Driven Initial Placement for FPGAs via Graph Matching, Proceedings of the SRC Techcon Conference, October 2005.
- Y. Xu, K. L. Hsiung, L. Pileggi, and S. Boyd, OPERA: OPtimization with Ellipsoidal uncertainty for Robust Analog IC design, Design Automation Conference, June 2005.
- Y. Zhan, X. Li, A. Strojwas, and L. Pileggi, Correlation-Aware Statistical Timing Analysis with Non-Gaussian Delay Distributions, Design Automation Conference, June 2005.
- V. Kheterpal, T. Hersan, V. Rovner, D. Motiani, Y. Takagawa, L. Pileggi and A. Strojwas, Design Methodology for IC Manufacturability Based on Regular Logic-Bricks, Design Automation Conference, June 2005.
- Y. Xu and L. Pileggi, Metal-mask Configurable RF Integrated Circuits, GOMACTech-05 Technical Program, April 2005.
- X. Li, K.Y. Tong, Y. Xu and L. Pileggi, Robust Optimization for Radiation Hardened Analog/RF Circuits, GOMACTech-05 Technical Program, April 2005.
- P. Li and L. Pileggi, Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction, Design and Test in Europe Conference (DATE), February 2005.
- S. Biswas, P. Li, S. Blanton and L. Pileggi, Specification Test Compaction for Analog Circuits and MEMS, Design and Test in Europe Conference (DATE), February 2005.
- R. Batra, P. Li, Y-T. Chen and L. Pileggi, A Methodology for Analog Circuit Macromodeling, IEEE International Workshop on Behavioral Modeling and Simulation, October 2004.
- R. Marculescu, D. Marculescu and L. Pileggi, Toward an Integrated Design Methodology Fault Tolerant, Multiple Clock/Voltage Integrated Systems, Proceedings of the International Conference on Computer Design, October 2004.
- V. Chandra, H. Schmit and L. Pileggi, A Power Aware System Level Interconnect Design Methodology for Latency-Insensitive, Proceedings of the International Conference on Computer-Aided Design, November 2004.
- P. Li, L. Pileggi, M. Ashegi, R. Chandra, Efficient Full-Chip Thermal Modeling and Analysis, Proceedings of the International Conference on Computer-Aided Design, November 2004.
- P. Li and L. Pileggi, Efficient Harmonic Balance Simulation Using Multi-Level Frequency Decomposition, Proceedings of the International Conference on Computer-Aided Design, November 2004.
- X. Li and L. Pileggi, Robust Analog/RF Circuit Design with Projection-Based Posynomial, Proceedings of the International Conference on Computer-Aided Design, November 2004.
- X. Li, J. Le, P. Gopalakrishnan and L. Pileggi, Asymptotic Probability Extraction for Non-Normal Distributions of Circuit Performance, Proceedings of the International Conference on Computer-Aided Design (Best Paper Award), November 2004.
- Y. Xu, C. Boone and L. Pileggi, Metal-mask configurable RF Front-end Circuits, in Proceedings of IEEE RFIC Symposium, June 2004.
- Satrajit Gupta and Larry Pileggi, Hierarchical Modeling of Magnetic Coupling, ACM/IEEE Design Automation Conference, June 2004.
- Veerbhan Kheterpal, Andrzej Strojwas, Larry Pileggi, Routing Architecture Exploration for Regular Fabrics, ACM/IEEE Design Automation Conference, June 2004.
- Jiayong Le, Xin Li and Larry Pileggi, STAC: Statistical Timing Analysis with Correlation, ACM/IEEE Design Automation Conference, June 2004.
- Yang Xu, Larry Pileggi, Stephan Boyd, ORACLE: Optimization with Recourse of Analog Circuits including Layout Extration, ACM/IEEE Design Automation Conference, June 2004.
- Xin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan and Lawrence Pileggi, A Frequency Relaxation Approach for Analog/RF System-Level Simulation, ACM/IEEE Design Automation Conference, June 2004.
- L. Pileggi and A.J. Strojwas, Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off, International Solid State Circuits Conference (invited presentation), February 2004.
- A. Koorapaty, V. Kheterapal, M. Fu, P. Gopalakrishnan and L. Pileggi, Exploring Logic Block Granularity for Regular Fabrics, Design and Test in Europe Conference (DATE), February 2004.
- V. Chandra, A. Xu, H. Schmit and L. Pileggi, An Interconnect Channel Design Methodology for High Performance Integrated Circuits, Design and Test in Europe Conference (DATE), February 2004.
- P. Li and L. Pileggi, Modeling Nonlinear Communication ICs Using a Multivariate Formulation, IEEE International Workshop on Behavioral Modeling and Simulation, October 2003.
- P. Li, X. Li, Y. Xu and L. Pileggi, A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits, Proceedings of the International Conference on Computer-Aided Design, November 2003.
- J. Le, A. Devgan and L. Pileggi, Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics, Proceedings of the International Conference on Computer-Aided Design, November 2003.
- H. Zheng, B. Krauter, L. Pileggi, On-Package Decoupling Optimization with Package Macromodels, Int’l Custom Integrated Circuits Conference, Sept. 2003.
- K.Y. Tong, V. Kheterapal, S. Rovner, H. Schmit, L. Pileggi, R. Puri, Regular Logic Fabrics for a Via Patterned Gate Array (VPGA), Int’l Custom Integrated Circuits Conference, Sept. 2003.
- A. Koorapaty, L. Pileggi, H. Schmit, Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics, International Conference on Field Programmable Logic and Applications, September 2003.
- S. Gupta and L. Pileggi, Hierarchical Modeling of Electrostatic and Magnetostatic Coupling, Proceedings of the SRC Techcon Conference, August 2003.
- X. Qi, G. Leonhardt, D. Flees, X-D, Yang, S. Kim, S. Mueller, H. Mau and L. Pileggi, Simulation Approach for Inductance Effects of VLSI Interconnects, In Proc. of the Great Lakes Symposium on VLSI, May 2003.
- D. Pandini, L. Pileggi, A. Strojwas, Bounding the Efforts on Congestion Optimization for Physical Synthesis, In Proc. of the Great Lakes Symposium on VLSI, May 2003.
- I. Bolsens, A. Broom, C. Hamlin, P. Magarshack, Z. Or-Bach and L. Pileggi, Fast, Cheap and Under Control: The Next Implementation Fabric, IEEE/ACM Design Automation Conference, June 2003.
- L. Pileggi, H. Schmit, A.J. Strojwas, et al, Exploring Regular Fabrics to Optimize the Performance-Cost Trade-Off, IEEE/ACM Design Automation Conference, June 2003.
- X. Li, P. Li, Y. Xu and L. Pileggi, Analog and RF Circuits Macromodels for System-Level Analysis, IEEE/ACM Design Automation Conference, June 2003.
- P. Li and L. Pileggi, NORM: Compact Model Order Reduction of Weakly Nonlinear Systems, IEEE/ACM Design Automation Conference (Best Paper Award), June 2003.
- C. Patel, A. Cozzie, H. Schmit and L. Pileggi, An Architecture Exploration of Via Patterned Gate Arrays, Internation Symposium on Physical Design, April 2003.
- E. Malley, A. Salinas, K. Ismail and L. Pileggi, Power Comparison of Throughput Optimized IC Busses, IEEE Symposium on VLSI, February, 2003.
- A. Koorapaty, V. Chandra, K.Y. Tong, C. Patel, L. Pileggi and H. Schmit, Heterogeneous Programmable Logic Block Architectures, Design and Test in Europe Conference (DATE), March 2003.
- Y. Xu and L. Pileggi, Noise Macromodel for Radio Frequency Integrated Circuits, Design and Test in Europe Conference (DATE), March 2003.
- X. Li and L. Pileggi, A Frequency Separation Macromodel for System-Level Simulation of RF Circuits, Asia-Pacific Design Automation Conference, February 2003.
- P. Li and L. Pileggi, Nonlinear Distortion Analysis Via Linear-Centric Models, Asia- Pacific Design Automation Conference, February 2003.
- M. Celik, H. Zheng and L. Pileggi, Efficient Reduction of Susceptance-Based Package Models Using PRIMA, Proceedings of the Topical Meeting on Electrical Performance of Electronic Packaging, October 2002.
- H. Zheng and L. Pileggi, Robust and Passive Model OrderReduction for Circuits Containing Susceptance Elements, Proceedings of the International Conference on Computer-Aided Design, November 2002.
- T. Lin and L. Pileggi, Throughput Driven IC Communication Synthesis, Proceedings of the International Conference on Computer-Aided Design, November 2002.
- A. Koorapaty and L. Pileggi, Modular, Fabric-specific Synthesis for Programmable Architectures, International Conference on Field Programmable Logic and Applications, September 2002, France.
- T. Lin, M. Beattie and L. Pileggi, On the Efficacy of Simplified 2D On-Chip Inductance Models, ACM/IEEE Design Automation Conference, June 2002.
- H. Zheng and L. Pileggi, Modeling and Analysis of Regular Symmetrically Structured Power/Ground Distribution Networks, ACM/IEEE Design Automation Conference, June 2002.
- D. Pandini, L. Pileggi and A. Strojwas, Understanding and Addressing the Impact of Wiring Congestion During Technology Mapping, Int’l Symposium on Physical Design (ISPD), April 2002.
- D. Pandini, L. Pileggi and A. Strojwas, Congestion-Aware Logic Synthesis, Design and Test in Europe Conference (DATE), March 2002.
- P. Li and L. Pileggi, A Linear-Centric Modeling Approach to Harmonic Balance Analysis, Design and Test in Europe Conference (DATE), March 2002.
- T. Lin, M. Beattie and L. Pileggi, On-Chip Inductance Models:3D or not 3D?, Design and Test in Europe Conference (DATE), March 2002.
- E. Acar, L. Pileggi and S. Nassif, A Linear-Centric Simulation Framework for Parametric Fluctuations, Design and Test in Europe Conference (DATE), March 2002.
- H. Zhang, B. Krauter, M. Beattie and L. Pileggi, Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses, Design and Test in Europe Conference (DATE), March 2002.
- E. Acar, S. Nassif and L. Pileggi, Time-Domain Simulation of Variational Interconnect Models, Int’l Symposium on Quality in Electronic Design, March 2002.
- Y-C. Lu, M. Celik, T. Young, and L. Pileggi, Min/Max On-Chip Inductance Models and Delay Metrics, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
- R. Arunachalam, R. D. Blanton and L. Pileggi, False coupling interactions in static timing analysis, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
- M. Beattie, L. Pileggi, Inductance 101 (Embedded Tutorial), Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
- M. Beattie, L. Pileggi, Modeling Magnetic Coupling for Gigascale Interconnect, Design Automation Conference (DAC) 2001, Las Vegas, June 2001.
- P. Gopalakrishnan, A. Odabasioglu, L. Pileggi and S. Raje, Overcoming Wireload Model Uncertainty During Physical Design, Int’l Symposium on Physical Design (ISPD), April 2001.
- T. Lin and L. Pileggi, RC(L)Interconnect Sizing With Second Order Considerations via Posynomial Programming, Int’l Symposium on Physical Design (ISPD), April 2001.
- M. Beattie and L. Pileggi, Efficient Inductance Extraction via Windowing, Design and Test in Europe Conference (DATE), March 2001.
- E. Acar, S. Nassif and L. Pileggi, Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations, Int’l Symposium on Quality in Electronic Design, March 2001.
- E. Acar, S. Nassif and L. Pileggi, Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations, ACM/IEEE Workshop on Timing in the Specification and Synthesis of Digital Systems, December 2000.
- M. Beattie, S. Gupta, L. Pileggi, Hierarchical Interconnect Circuit Models, Proceedings of the International Conference on Computer-Aided Design, November 2000.
- R. Arunachalam and L.T. Pileggi, Can We Continue to Predict Timing of ICs Prior to Manufacturing as Technologies Continue to Scale?, ISD Magazine, September 2000.
- T. Lin and L. Pileggi, RC(L) Interconnect Sizing with Second Order Considerations, Proceedings of the SRC Techcon Conference, September 2000.
- R. Arunachalam, K. Rajagopal and L. Pileggi, TACO: Timing Analysis with Coupling, Proceedings of the Design Automation Conference, June 2000.
- Y. Liu, S. Nassif, L. Pileggi and A.J. Strojwas, Impact of interconnect variations on the clock skew of a gigahertz microprocessor, Proceedings of the Design Automation Conference, June 2000.
- M. Beattie and L. Pileggi, Electromagnetic Parasitic Extraction via a Multipole Method with Hierarchical Refinement, Proceedings of the International Conference on Computer-Aided Design, November 1999.
- A. Odabasioglu, M. Celik & L. T. Pileggi, Practical Considerations for Passive Reduction of RLC Circuits, Proceedings of the International Conference on Computer- Aided Design, November 1999.
- A. Odabasioglu, M. Celik & L. T. Pileggi, Efficient and Accurate Delay Metrics for RC Interconnect, PATMOS: International Workshop on Power and Timing Modeling, Optimization and Simulation, October 1999.
- Y. Liu, L. Pileggi and A.J. Strojwas, Model Order-Reduction of RC(L) Interconnect including Variational Analysis, Proceedings of the Design Automation Conference (Best Paper Award Nomination), June 1999.
- M. Beattie and L. Pileggi, IC Analyses Including Extracted Inductance Models, Proceedings of the Design Automation Conference, Invited Paper, June 1999.
- L. Pileggi, Achieving Timing Closure for Giga-Scale IC Designs, 1999 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Invited Paper, March 1999.
- E. Acar, A. Odabasioglu, M. Celik and L. Pileggi, S2P: Stable 2-Pole Model for RC Interconnect Delay Analysis, Proceedings of the 9th Great Lakes Symposium on VLSI, March 1999.
- M. Beattie, L. Alatan and L. Pileggi, Equipotential Shells for Efficient Partial Inductance Extraction, Proceedings of the International Electronics Devices Meeting, December 1998.
- P. Gross, R. Arunachalam, K. Rajagopal and L. Pileggi, Determination of Worst-Case Aggressor Alignment for Delay Calculation, Proceedings of the International Conference on Computer-Aided Design, November 1998.
- T. Lin, Emrah Acar and L. Pileggi, h-gamma: An Interconnect Timing Metric Based on the Gamma Distribution Model for the Homogeneous Response, Proceedings of the International Conference on Computer-Aided Design, November 1998.
- F. Liu, L. Pileggi and A.J. Strojwas, A Synthesized Driving-Point Model for Capacitively Coupled Interconnects, Proceedings of the SRC Techcon Conference, September 1998.
- K. Rajagopal, P. Gross and L. Pileggi, The Impact of Coupling on Worst-Case Waveform Analysis, Proceedings of the SRC Techcon Conference, September 1998.
- T. Lin and L. Pileggi, Looking Beyond the Elmore Delay — Metrics for Deep Submicron, Proceedings of the SRC Techcon Conference, September 1998.
- M. Beattie and L. Pileggi, Equipotential Shells for Efficient Inductance Extraction, Proceedings of the SRC Techcon Conference, September 1998.
- Florin Dartu and Lawrence Pileggi, TETA: Transistor-Level Engine for Timing Analysis, Proceedings of the Design Automation Conference, June 1998.
- Frank Liu, Lawrence Pileggi and Andrzej Strojwas, ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models, Proceedings of the Design Automation Conference, June 1998.
- Rony Kay and Lawrence Pileggi, PRIMO: Probability Interpretation of Moments for Delay Calculation, Proceedings of the Design Automation Conference, June 1998.
- L. Pileggi, Timing Metrics for Physical Design of Deep Submicron Technologies, Invited paper, International Symposium on Physical Design, April 1998.
- Zhijiang (John) He and Lawrence T. Pileggi, A Simple Algorithm for Calculating Frequency-Dependent Inductance Bounds, Proceedings of the Custom Integrated Circuits Conference, May 1998.
- G. Ellis, L.T. Pileggi, R.A. Rutenbar, A Hierarchical Decomposition Methodology for Multistage Clock Circuits, Proceedings of the International Conference on Computer-Aided Design, 1997.
- A. Odabasioglu, M. Celik, L.T. Pileggi, PRIMA: Passive Reduced-order Interconnect Macromodeling Algorithm, Proceedings of the International Conference on Computer-Aided Design, 1997.
- A. Mehta, Y-P. Chen, N. Menezes, L. T.Pileggi and M. Wong, Clustering and Load Balancing for Buffered Clock Tree Synthesis, Proceedings of the Int’l Conference on Computer Design, October 1997.
- Ravishankar Arunachalam, Florentin Dartu and Lawrence T.Pileggi, CMOS Gate Delay Models for General RLC Loading, Proceedings of the Int’l Conference on Computer Design, October 1997.
- John He, Mustafa Celik and Lawrence Pileggi, SPIE: Sparse PEEC Inductance Extraction, Proceedings of the Design Automation Conference, 1997.
- Michael Beattie and Lawrence Pileggi, Bounds for BEM Capacitance Extraction, Proceedings of the Design Automation Conference, 1997.
- Florin Dartu and Lawrence Pileggi, Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling, Proceedings of the Design Automation Conference, 1997.
- R. Kay, G. Bucheuv, and L. Pileggi, EWA: Exact Wire Sizing Algorithm, 1997 International Symposium on Physical Design, April 1997.
- G. Ellis, L. Pileggi and R. Rutenbar, A Hierarchical Decomposition Methodology for Single-Stage Clock Circuits, Proceedings of the Custom Integrated Circuits Conference, May 1997.
- F. Liu, L. Pileggi and A.J. Strojwas, A Sparse Macromodeling Method for RC Interconnect Multiports, Proceedings of the Custom Integrated Circuits Conference, May 1997.
- F. Dartu and L.T. Pileggi, Gate-level modeling of of coupling capacitance effects, Proceedings of the SRC Techcon Conference, October 1996.
- Florentin Dartu and Lawrence T. Pileggi, Modeling Signal Waveshapes for Empirical CMOS Gate Delay Models, Sixth International Workshop on Power and Timing Modeling, Optimization and Simulation, September 1996.
- Florin Dartu, Bogdan Tutuianu and Lawrence T. Pileggi, RC-Interconnect Macromodels for Timing Simulation, Proceedings of the Design Automation Conference , 1996.
- Bogdan Tutuianu and Lawrence Pileggi, An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response, Proceedings of the Design Automation Conference , 1996.
- Byron Krauter, Yu Xia, Aykut Dengi, Lawrence T. Pileggi, A Sparse Image Method for BEM Capacitance Extraction, Proceedings of the Design Automation Conference, 1996.
- Xun Yang, Byron Krauter and L. Pileggi, Combined ac and Transient Power Distribution Analysis, Proceedings of the Custom Integrated Circuits Conference, May 1996.
- R. Gupta, B. Krauter and L. Pileggi, On Moment Based Metrics for Optimal Termination of Transmission Line Interconnects, Proceedings of the 9th International Conference on VLSI Design, January 1996.
- M. Kamon, B. Krauter, J. Phillips, L. Pileggi, and J. White, Two Optimizations to Accelerated Method-of-Moments Algorithms for Signal Integrity Analysis of Complicated 3-D Packages, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, November, 1995.
- R. Gupta and L. Pileggi, Constrained Multivariable Optimization of Transmission Lines with General Topologies, Proceedings of the International Conference on Computer-Aided Design, 1995.
- N. Menezes, R. Baldick and L. Pileggi, A Sequential Quadratic Programming Approach to Concurrent Gate and Wire Sizing, Proceedings of the International Conference on Computer-Aided Design, 1995.
- B. Krauter and L. Pileggi, Generating Sparse Partial Inductance Matrices with Guaranteed Stability, Proceedings of the International Conference on Computer-Aided Design, 1995.
- L. Pileggi, Coping with RC(L) Interconnect Induced Headaches, Proceedings of the International Conference on Computer-Aided Design, (Invited Tutorial Paper) 1995.
- I. Tesu and L. Pileggi, Pre-characterization of ECL Gates for Timing Analysis, SCS ’95 International Symposium on Signals, Circuits & Systems, Iasi, Romania, October 19-21, 1995.
- I. Tesu and L. Pileggi, Timing Analysis Models for Gates and Cells with Bipolar Transistor Output Stages, Proceedings of the IEEE ASIC Conference, 1995.
- B. Krauter, R. Gupta, J. Willis and L. Pileggi, Transmission Line Synthesis, Proceedings of the Design Automation Conference , 1995.
- N. Menezes, S. Pullela and L. Pileggi, Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization, Proceedings of the Design Automation Conference, 1995.
- R. Gupta, B. Krauter, B. Tutuianu, J. Willis and L. Pileggi, “The Elmore Delay as a Bound for RC-Trees with Generalized Input Signals,” Proceedings of the Design Automation Conference, 1995.
- S. Pullela, N. Menezes and L.T. Pillage, Low Power IC Clock Tree Design, Proceedings Custom Integrated Circuits Conference, May 1995.
- B. Krauter, D. Neikirk and L.T. Pillage, Sparse Partial Inductance Matrix Formulation, Progress in Electromagnetics Research Symposium, July 1995.
- Rohini Gupta, John Willis and L.T. Pillage, Wire Width Optimization of Transmission Lines for Low Power Design, IEEE Multi-chip Module Conference, February, 1995.
- L.T. Pillage and R.A. Rohrer, The Essence of AWE, Circuits and Devices Magazine, November 1994.
- John Willis, Rohini Gupta and L.T. Pillage, Metrics for RLC Transmission Line Termination, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, November, 1994.
- N. Menezes, S. Pullela and L.T. Pillage, RC Interconnect Synthesis — A Moment Fitting Approach, Proceedings of the 1994 International Conference on Computer-Aided Design, Nov. 1994.
- R. Gupta, S.Y. Kim and L.T. Pillage, Domain Characterization of Transmission Line Models for Efficient Simulation, Proceedings of the International Conference on Computer Design, October 1994.
- R. Gupta and L.T. Pillage, OTTER: Optimal Termination of Transmission Lines Excluding Radiation, Proceedings Design Automation Conference, June 1994.
- F. Dartu, N. Menezes, J. Qian and L.T. Pillage, A Gate Delay Model for High Performance CMOS, Proceedings Design Automation Conference, June 1994.
- R.B. Brashear, N. Menezes, C. Oh, L.T. Pillage and M.R. Mercer, Predicting Circuit Performance Using Circuit-Level Statistical Timing Analysis, Proceedings of the European Design Automation Conference, February 1994.
- S. Y. Kim, E. Tuncer, R. Gupta, B. Krauter, T.L. Savarino, D. P. Neikirk and L. T. Pillage, An Efficient Methodology for Extraction and Simulation of Transmission Lines for Application Specific Electronic Modules, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.
- S. Pullela, N. Menezes and L.T. Pillage, Skew and Delay Optimization for Reliable Buffered Clock Trees, Proceedings of the 1993 International Conference on Computer-Aided Design, Nov. 1993.
- E. Tuncer, S.Y. Kim, L.T. Pillage and D. Neikirk, A New, Efficient Circuit Model for Microstrip Lines Including Both Current Crowding and Skin Depth Effects, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, October, 1993.
- D.C. Yuan, L.T. Pillage, and J.T. Rahmeh, Evaluation by Parts of Mixed-Level dc- Connected Components in Logic Simulation, Proceedings Design Automation Conference, June 1993.
- S. Pullela, N. Menezes and L.T. Pillage, Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization, Proceedings Design Automation Conference, June 1993.
- N. Menezes, S. Pullela, A. Balivada and L.T. Pillage, Skew Reduction in Clock Trees Using Wire Width Optimization, Proceedings Custom Integrated Circuits Conference, May 1993.
- V. Raghavan, R.A. Rohrer, L.T. Pillage, J.Y. Lee, J.E. Braken, M.M. Alaybeyi, AWE-Inspired, Proceedings Custom Integrated Circuits Conference, (Invited Tutorial Paper) May 1993.
- S.Y. Kim, N. Gopal and L.T. Pillage, Finite-Pole Macromodels of Transmission Lines for Circuit Simulation, Proceedings Custom Integrated Circuits Conference, May 1993.
- R. Brashear, D. Holberg, M.R. Mercer and L.T. Pillage, ETA: Electrical-Level Timing Analysis, Proceedings IEEE International Conference on Computer-Aided Design, November 1992.
- S.Y. Kim, N. Gopal and L.T. Pillage, AWE Macromodels for Incorporation in a Circuit Simulator, Proceedings IEEE International Conference on Computer-Aided Design, November 1992.
- M. Becker, D. Beer, M.J. Gonzalez, C.M. Maziar, L.T. Pillage, M.D. Shermis, T.J. Wagner and G.L. Wise, Introduction to Electrical and Computer Engineering, Proceedings of the 1992 American Society on Engineering Education Annual Conference.
- D. F. Anastasakis, N. Gopal, S.Y. Kim and L.T. Pillage, On the Stability of Moment Matching Approximations in Asymptotic Waveform Evaluation, Proceedings Design Automation Conference, June 1992.
- C. Ratzlaff, S. Pullela and L.T. Pillage, Effects of RC-Interconnect in a Hierarchical Timing Analyzer, Proceedings Custom Integrated Circuits Conference, May 1992.
- N. Gopal, E. Tuncer, D. Neikirk and L.T. Pillage, Non-Uniform Models for Transmission Line Analysis, IEEE Sponsored Topical Meeting on Electrical Performance of Electronic Packaging, April, 1992.
- N. Gopal, D. Neikirk and L.T. Pillage, Evaluating RC Interconnect Using Moment Methods, Proceedings IEEE International Conference on Computer-Aided Design, November 1991.
- N. Gopal, C. Ratzlaff, L.T. Pillage, Constrained Approximation of Dominant Time Constants in RC Circuit Delay Models, Proceedings of the International Mathematics and Computation Symposium, (Invited Paper) July 1991.
- C. Ratzlaff, N. Gopal, L.T. Pillage, RICE: Rapid Interconnect Circuit Evaluator, Proceedings Design Automation Conference, (Best Paper Award Nomination), June 1991.
- A. Balivada, D. Holberg and L.T. Pillage, Calculation and Application of Time-Domain Sensitivities in Asymptotic Waveform Evaluation, Proceedings Custom Integrated Circuits Conference, May 1991.
- D. Holberg, S. Dutta and L.T. Pillage, DC Parametrized Piecewise Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation, Proceedings IEEE International Conference on Computer-Aided Design, November 1990.
- S. Dutta and L.T. Pillage, Calculating the Moments in AWE With Linear Complexity, Proceedings of the SRC Techcon Conference, October 1990.
- L.T. Pillage and S. Dutta, A Path Tracing Algorithm for Asymptotic Waveform Evaluation of RLC Circuit Delay Models, 1990 ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, August 1990.
- L.T. Pillage, X. Huang and R.A. Rohrer, Asymptotic Waveform Evaluation for Circuits Containing Floating Nodes, Proceedings IEEE International Symposium on Circuits and Systems, May 1990.
- L.T. Pillage, X. Zhang and R.A. Rohrer, Efficient Final Placement Based on Nets-as- Points, Proceedings Design Automation Conference, June 1989.
- L.T. Pillage, X. Huang and R.A. Rohrer, AWEsim: Asymptotic Waveform Evaluation for Timing Analysis, Proceedings Design Automation Conference, June 1989.
- L.T. Pillage, C. Wolff and R.A. Rohrer, Frequency Response Simulation, Proceedings Custom Integrated Circuits Conference, May 1989.
- L.T. Pillage and R.A. Rohrer, Delay Evaluation with Lumped Linear RLC Interconnect Circuit Models, Proceedings Decennial Caltech Conference on VLSI, March 1989.
- L.T. Pillage and R.A. Rohrer, A Quadratic Metric for the Initial Placement Problem with a Simple Solution Scheme, Proceedings Design Automation Conference, June 1988.
- L.T. Pillage, X. Huang and R.A. Rohrer, TALISMAN: A Piecewise Linear Circuit Simulator Based on Tree Link Analysis, Proceedings IEEE International Conference on Computer-Aided Design, November 1987.
- L.T. Pillage, X. Huang and R.A. Rohrer, Tree Link Partitioning for the Implicit Solution of Circuits, Proceedings IEEE International Symposium on Circuits and Systems, May 1987.

### Contact

Carnegie Mellon University

Hamerschlag Hall, 2113

5000 Forbes Avenue

Pittsburgh, PA 15213-3891 USA

pileggi@andrew.cmu.edu

Phone: 412-268-6774