1. S. Liu, T. Rabuske, J. Paramesh, L. Pileggi, and J. Fernandes, “Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs,” IEEE Transactions on Circuits and Systems I, To Appear.
  2. M. Darwish, V. Calayir, L. Pileggi, J. Weldon, “Ultra-Compact Graphene Multigate Variable Resistor for Neuromorphic Computing,” IEEE Transactions on Nanotechnology, Vol. 15, No. 2, March 2016.
  3. R. Liu, L. Pileggi and J. A. Weldon, “A Wideband RF Receiver with Extended Statistical Element Selection Based Harmonic Rejection Calibration”, Integration the VLSI Journal, June 2015.
  4. T. C. Jackson, A. A. Sharma, J. A. Bain, J. A. Weldon, L. Pileggi, “Oscillatory Neural Networks based on TMO Nano-Oscillators and Multi-Level RRAM Cells,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), June 2015.
  5. V. Calayir and L. Pileggi, “Device Requirements and Technology-driven Architecture Optimization for Analog Neurocomputing,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 5, no. 2, pp. 162-173, June 2015.
  6. R. Liu and L. Pileggi, “Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC,” IEEE Transactions on Circuits and Systems II, vol 62, no. 7, pp. 651-655, Jul. 2015.
  7. K. Vaidyanathan, R. Liu, L. Liebmann, K. Lai, A. Strojwas, L. Pileggi, Design Implications of Extremely Restricted Patterning, Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol 13 (03), 2014.
  8. K. Vaidyanathan, Q. Zhu, L. Liebmann, K. Lai, S. Wu, R. Liu, Y. Liu, A.J. Strojwas, and L. Pileggi, “Exploiting Sub-20 nm CMOS Technology Challenges to Design Affordable SoCs,” Journal of Micro/Nanolithography, J. Micro/Nanolith. MEMS MOEMS, 14(1), 011007 (2015).
  9. D. M. Bromberg, H. E. Sumbul, J.-G. Zhu, L. Pileggi, “All-Magnetic MRAM Based on Four Terminal mCell Device,” Journal of Applied Physics, May 2015.
  10. V. H-C. Chen and L. Pileggi, “A 69.5mW 20GS/s 6b Time-Interleaved ADC with Embedded Time-to-Digital Calibration in 32nm CMOS SOI,” Special Issue of the IEEE Journal on Solid State Circuits (Invited Paper), vol.49, no.12, pp.2891,2901, Dec. 2014.
  11. S. Sun, F. Wang, S. Yaldiz, X. Li, L. Pileggi, A. Natarajan, M. Ferriss, J.-O. Plouchart, B. Sadhu, B. Parker, A. Valdes Garcia, M.A.T. Sanduleanu, J. Tierno, and D. Friedman, “Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits,” IEEE Transactions on Circuits and Systems, vol.61, no.8, pp.2243,2252, Aug. 2014.
  12. C.Y. Wen, G. Slovin, J. Bain, E. Schlesinger, L. Pileggi and J. Paramesh, “A Phase-Change Via-Reconfigurable CMOS LC VCO,” IEEE Transactions on Electron Devices, Vol. 60, No. 12, pp 3979-3988, December 2013.
  13. D.H. Morris, D.M. Bromberg, J-G. ZHU and L. Pileggi, Spintronic Devices and Circuits for Low-Voltage Logic, International Journal of High Speed Electronics and Systems Vol. 21, No. 1 (2012) 1250005.
  14. B. Sadhu, M.A. Ferriss, A.S. Natarajan, S. Yaldiz, J-O. Plouchart, A.V. Rylyakov, A. Valdes-Garcia, B.D. Parker, A. Babakhani, S. Reynolds, X. Li, L. Pileggi, R. Harjani, J. Tierno and D. Friedman, A Linearized Low Noise VCO-Based PLL With Automatic Biasing, IEEE Journal of Solid State Circuits (Invited), Volume 48 , Issue 5, May 2013.
  15. D. Bromberg, D. Morris, L. Pileggi and J. Zhu, All-Magnetic, Nonvolatile, Addressable Chainlink Memory, IEEE Transactions on Magnetics, vol. 49, no. 7, 2013.
  16. V. Sokalski, D. Bromberg, D. Morris, M. T. Moneck, E. Yang, L. Pileggi, and J-G. Zhu, “Naturally Oxidized FeCo as a Magnetic Coupling Layer for Electrically Isolated Read/Write Paths in mLogic,” IEEE Transactions on Magnetics, vol. 49, no. 7, 2013.
  17. Q. Zhu, C. Berger, E. Turner, L. Pileggi and F. Franchetti, Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation, Journal of Signal Processing Systems, Accepted for publication.
  18. M. Althoff, A. Rajhans, B. Krogh, S. Yaldiz, X. Li, and L. Pileggi, Formal Verification of Phase-Locked Loops Using Reachability Analysis and Continuization, Communications of the ACM (invited paper), 2012.
  19. D. Bromberg, D. Morris, L. Pileggi, J.-G. Zhu, “Novel STT-MTJ device enabling all-metallic logic circuits,” IEEE Transactions on Magnetics, INTERMAG 2012.
  20. Gokce Keskin, Jon Proesel and Larry Pileggi, 8-bit Flash ADC Design Based on Post-Manufacturing Statistical Element Selection, IEEE Journal of Solid State Circuits (Invited), Volume 46 , Issue 8, May 2011.
  21. Tejas Jhaveri, Vyacheslav Rovner, Lars Liebmann, Larry Pileggi, Andrzej Strojwas, Jason D. Hibbeler, Design Technology Co-optimization for Predictive Technology Scaling Beyond Gratings, Invited Keynote Paper, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 4, April 2010.
  22. Xin Li, Yaping Zhan and Lawrence Pileggi, Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 5, pp. 831-843, May 2008.
  23. Xin Li, Jiayong Le, Mustafa Celik and Lawrence Pileggi, Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 6, pp. 1041-1054, Jun. 2008.
  24. Benton Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence Pileggi, Rob Rutenbar and Kenneth Shepard, “Digital circuit design challenges and opportunities in the era of nanoscale CMOS,” Proceedings of The IEEE (PTI), vol. 96, no. 2, pp. 343-365, Feb. 2008.
  25. Xin Li, Jiayong Le, Lawrence Pileggi, “Statistical Performance Modeling and Optimization”, Foundations and Trends in Electronic Design Automation: Vol. 1: No 4, pp 331-480, 2007.
  26. Tejas Jhaveri, Vyacheslav Rovner, Larry Pileggi, Andrzej J. Strojwas, et al., “Maximization of Layout Printability/Manufacturability by Extreme Layout Regularity”, Journal of Micro/Nanolithography, MEMS, and MOEMS, Vol 6 (03), 2007.
  27. Xin Li, Jiayong Le, Padmini Gopalakrishnan and Lawrence Pileggi, “Asymptotic probability extraction for non-Normal performance distributions,” IEEE Trans. on Computer-Aided Design of Integrated Circuits (TCAD), January 2007.
  28. Xin Li, Padmini Gopalakrishnan, Yang Xu and Lawrence Pilegg, “Robust analog/RF circuit design with projection-based performance modeling,” IEEE Trans. on Computer-Aided Design of Integrated Circuits (TCAD), January 2007.
  29. P. Li, L. Pileggi, M. Ashegi, R. Chandra, Efficient Full-Chip Thermal Modeling and Analysis, IEEE Transactions on CAD, Vol. 25, Issue 9, pp. 1763 – 1776, Sept. 2006.
  30. Yang Xu, Larry Pileggi, Stephan Boyd, ORACLE: Optimization with Recourse of Analog Circuits including Layout Extraction, Accepted to IEEE Transactions on CAD.
  31. P. Li and L. T. Pileggi, Compact Reduced-Order Modeling of Weakly Nonlinear Analog and RF Circuits, IEEE Transactions on Computer-Aided Design, Vol. 23, No. 2, pp. 184-203, February 2005.
  32. Y. Xu, C. Boone and L. Pileggi, Metal-mask configurable RF Front-end Circuits, IEEE Journal of Solid State Circuits, Volume: 39, Issue: 8, pp. 1347-1351, Aug. 2004.
  33. H. Zheng, B. Krauter and L.T. Pileggi, Electrical Modeling of Integrated-Package Power/Ground Distributions, IEEE Design and Test, Volume: 20 Issue: 3, pp. 23-31, May-June 2003.
  34. M. Beattie and L.T. Pileggi, Parasitic Extraction with Multipole Refinement, IEEE Transactions on Computer-Aided Design, Vol. 23, (5 pages), February 2004.
  35. P. Li and L. T. Pileggi, Efficient Per-Nonlinearity Distortion Analysis for Analog and RF Circuits, IEEE Transactions on Computer-Aided Design, Vol. 22, No. 10, pp. 1297-1309, October 2003.
  36. D. Pandini, L. T. Pileggi and A.J. Strojwas, Global and Local Congestion Optimization in Technology Mapping, IEEE Transactions on Computer-Aided Design, Vol. 22, No. 4, pp. 498-506, April 2003.
  37. R. Arunachalam, R. D. Blanton, L. T. Pileggi, “Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation,” VLSI Design (Special Issue on TimingAnalysis and Optimization for DSM ICs), Vol.15, pp. 605-618, 2002.
  38. E. Acar, F. Dartu and L. T. Pileggi, TETA: Transistor level Waveform Evaluation for Timing Analysis, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 5, May 2002.
  39. M. Beattie and L.T. Pileggi, On-Chip Induction Modeling: Basics and Advanced Methods, Special Issue of IEEE Transactions on VLSI Systems, vol. 10, No. 6, pp. 712-729, December 2002.
  40. P. Gopalakrishnan, A. Odabasioglu, L. T. Pileggi, and S. Raje, Overcoming Wireload Model Uncertainty for Physical Design, IEEE Transactions on Computer-Aided Design, Vol. 21, No. 1, January, 2002.
  41. R.E. Bryant, K.T. Cheng, A.B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. Rabaey and A. Sangiovanni-Vincentelli, Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI, Proceedings of the IEEE, Special Issue on the Limits of Semiconductor Technology, pp. 341-366, March 2001.
  42. Y. Liu, L. T. Pileggi and A.J. Strojwas, ftd: Frequency to Time Domain Conversion for Reduced Order Interconnect Circuits, IEEE Transactions on Circuits and Systems, April 2001.
  43. M. Beattie, B. Krauter, L. Alatan and L. Pileggi, Equipotential Shells for Efficient Inductance Extraction, IEEE Transactions on Computer-Aided Design, Vol. 20, No. 1, January 2001.
  44. M. Celik and L. T. Pileggi, Metrics and Bounds for Phase Delay and Signal Attenuation in RCL Clock Trees, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 293-300, March 1999.
  45. M. Beattie and L. T. Pileggi, Bounds for BEM Capacitance Extraction, IEEE Transactions on Computer-Aided Design, Vol. 18, No. 3, pp. 311-321, March 1999.
  46. Rohini Gupta, John Willis and L.T. Pileggi, Analytic Termination Metrics for Pin-to- Pin Lossy Transmission Lines with Nonlinear Drivers, IEEE Transactions on VLSI Systems, Vol. 6, No. 3, pp. 457-463, September 1998.
  47. A. Odabasioglu, M. Celik and L. T. Pileggi, PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm, IEEE Transactions on Computer-Aided Design (1999 IEEE Best Paper Award), Vol. 17, No. 8, pp. 645-654, August 1998.
  48. R. Kay and L. Pileggi, EWA: Efficient Wire Sizing Algorithm, IEEE Transactions on Computer-Aided Design, January, 1998.
  49. M. Celik and L. T. Pileggi, Simulation of Lossy Multiconductor Transmission Lines Using Backward Euler, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 45, No. 3, pp. 238-243, March 1998.
  50. N. Menezes, R. Baldick and L.T. Pileggi, A Sequential Quadratic Programming Approach to Concurrent Gate and Interconnect Sizing, IEEE Transactions on Computer- Aided Design, August 1997.
  51. S. Pullela, N. Menezes and L.T. Pileggi, Moment-Sensitivity-Based Wire Sizing for Skew Reduction in On-Chip Clock Nets, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 2, pp. 210-215, February 1997.
  52. Rohini Gupta, Byron Krauter and Lawrence Pileggi, Transmission Line Synthesis via Constrained Multivariable Optimization, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 6-19, January 1997.
  53. Rohini Gupta, Bogdan Tutuianu and Lawrence Pileggi, The Elmore Delay as a Bound for RC Trees with Generalized Input Signals, IEEE Transactions on Computer-Aided Design, Vol. 16, No. 1, pp. 95-104, January 1997.
  54. Rohini Gupta and Lawrence Pileggi, Modeling Lossy Transmission lines Using the Method of Characteristics, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 43, No. 7, pp. 580-583, July 1996.
  55. S. Pullela, N. Menezes and L.T. Pileggi, Post-Processing of Clock Trees via Wiresizing and Buffering for Robust Design, IEEE Transactions on Computer-Aided Design, pp. 691-701, June 1996.
  56. Rohini Gupta, John Willis and Lawrence T. Pileggi, Low Power Design of Off-Chip Drivers and Transmission lines: A Branch and Bound Approach, International Journal of High Speed Electronics and Systems, Vol. 7, no. 9, pp. 27-45, June 1996.
  57. F. Dartu, N. Menezes and L.T. Pileggi, Performance Computation for Pre-characterized CMOS Gates with RC Loads, IEEE Transactions on Computer-Aided Design, pp. 544-553, May 1996.
  58. Rohini Gupta, Seok-Yoon Kim and Lawrence Pileggi, Domain Characterization of Transmission Line Models and Analyses, IEEE Transactions on Computer-Aided Design, pp. 184-193, February 1996.
  59. J. Qian, S. Pullela and L.T. Pillage, Modeling the “Effective Capacitance” of RC Interconnect, IEEE Transactions on Computer-Aided Design, pp. 1526-1535, December 1994.
  60. S.Y. Kim, N. Gopal and L.T. Pillage, Time-Domain Macromodels for VLSI Interconnect Analysis, IEEE Transactions on Computer-Aided Design, pp. 1257-1270, October 1994.
  61. C. Ratzlaff and L.T. Pillage, RICE: Rapid Interconnect Circuit Evaluation Using Asymptotic Waveform Evaluation, IEEE Transactions on Computer-Aided Design, pp. 763-776, June 1994.
  62. D.F. Anastaskis, N. Gopal, S.Y. Kim and L.T. Pillage, On the Stability of Moment- Matching Approximations in Asymptotic Waveform Evaluation, IEEE Transactions on Computer-Aided Design, pp. 729-736, June 1994.
  63. N. Gopal, A. Balivada and L.T. Pillage, Moment-Matching Approximations for Linear(ized) Circuit Analysis, Semiconductors in IMA Volumes in Mathematics and it’s Applications, F. Odeh, J. Cole, W. M. Coughran, Jr., P. Lloyd, and J. White, editors, Springer-Verlag, pp. 115-130, 1994.
  64. Lawrence T. Pillage, An Early Introduction to Circuit Simulation Techniques, IEEE Transactions on Education, February, 1993.
  65. L.T. Pillage and R.A. Rohrer, Asymptotic Waveform Evaluation, IEEE Transactions on Computer-Aided Design (1991 IEEE Best Paper Award), pp. 352-366, April 1990.