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  2. U.S. Patent No. 9,300,301 – A Non-Volatile Magnetic Logic Device –Bromberg, Zhu, Pileggi, Sokalski, Moneck, March 29, 2016.
  3. U.S. Patent No. 9,286,216 – 3DIC Memory Chips Including Computational Logic-in-Memory for Performing Accelerated Data Processing – Franchetti, Zhu and Pileggi, March 15, 2016.
  4. U.S. Patent No. 9,117,523 – Chainlink Memory – Morris, Bromberg, Pileggi, Zhu, August 25, 2015.
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  10. U.S. Patent No. 8,082,137 – Method and apparatus for thermal modeling and analysis of semiconductor chip designs  – Li, Pileggi, Asheghi and Chandra, December 20, 2011.
  11. U.S. Patent No. 7,945,868 – Tunable Integrated Circuit Design for Nano-Scale Technologies – Pileggi and Li, May 17, 2011.
  12. U.S. Patent No. 7,908,131 – Analog and radio frequency (RF) system-level simulation using frequency relaxation – Li, Li and Pileggi, March 15, 2011.
  13. U.S. Patent No. 7,906,254 – “Method and Process for Design of Integrated Circuits Using Regular Geometry Patterns to Obtain Geometrically Consistent Component Features” – Pileggi, Strojwas and Lanza, March 15, 2011.
  14. U.S. Patent No. 7,827,516 – Method and System for Grouping Logic in an Integrated Circuit Design to Minimize Number of Transistors and Number of Unique Geometry Patterns – Moe, Pileggi, et al, November 2, 2010.
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  19. U.S. Patent No. 7,634,248 – Configurable Circuits Using Phase Change Switches – Xu, Pileggi and Asheghi, December 15, 2009.
  20. U.S. Patent No. 7,487,486 – Defining Statistical Sensitivity for Timing Optimization of Logic Circuits with Large-Scale Process and Environmental Variations – Celik, Le, Pileggi and Li, February 3, 2009.
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  22. U.S. Patent No. 7,350,164 – Optimization and Design Method For Configurable Analog circuits And Devices – Xu, Pileggi and Boyd, March 2008.
  23. U.S. Patent No. 7,325,180 – System and Method to Test Integrated Circuits on a Wafer – Pileggi, Yue, Blanton and Vogels, January 2008.
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