Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography

Q. Zhu, L. Pileggi and F. Franchetti, Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography, Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 2012.

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS

J.-O. Plouchart, M. Ferriss, A. Natarajan, A. Valdes-Garcia, B. Sadhu, A. Rylyakov, B. Parker, M. Beakes, A. Babakani, S. Yaldiz, L. Pileggi, R. Harjani, S. Reynolds, J. A. Tierno, D. Friedman, “A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS”, Int’l Custom Integrated Circuits Conference, Sept. 2012.

Smart Memory Synthesis for Energy-Efficient Computed Tomography Reconstruction

Q. Zhu, L. Pileggi and F. Franchetti, “Smart Memory Synthesis for Energy-Efficient Computed Tomography Reconstruction”, Proceedings of the SRC Techcon Conference, September 2012.

Design Automation Framework for Application-Specific Logic-in-Memory Blocks

Q. Zhu, K. Vaidyanathan, O. Shacham, M. Horowitz, L. Pileggi and F. Franchetti, “Design Automation Framework for Application-Specific Logic-in-Memory Blocks”, IEEE International Conference on Application-specific Systems, Architectures and Processors, July 2012.

A 21.8-27.5GHz PLL in 32nm SOI Using Gm Linearization to Achieve -130dBc/Hz Phase Noise at 10MHz Offset from a 22GHz Carrier

B. Sadhu, M.A. Ferriss, J-O. Plouchart, A.S. Natarajan, A.V. Rylyakov, A. Valdes-Garcia, B.D. Parker, S. Reynolds, A. Babakhani, S. Yaldiz, L. Pileggi, R. Harjani, J. Tierno and D. Friedman, “A 21.8-27.5GHz PLL in 32nm SOI Using Gm Linearization to Achieve -130dBc/Hz Phase Noise at 10MHz Offset from a 22GHz Carrier”, 2012 Radio Frequency Integrated Circuits Symposium, June 2012.

Magnetic Logic Circuits with Minimal Connections to CMOS

D. Morris, D. Bromberg, J. Zhu and L. Pileggi, “Magnetic Logic Circuits with Minimal Connections to CMOS”, IEEE CAS-FEST, 2012.

mLogic: Ultra-Low Voltage Non-Volatile Logic Circuits Using STT-MTJ Devices

D. Morris, D. Bromberg, J. Zhu and L. Pileggi, “mLogic: Ultra-Low Voltage Non-Volatile Logic Circuits Using STT-MTJ Devices”, IEEE/ACM Design Automation Conference (DAC), 2012.

Spintronic Circuits and Devices for Low-Voltage Electronics

D. Morris, D. Bromberg, J. Zhu, and L. Pileggi, “Spintronic Circuits and Devices for Low-Voltage Electronics”, (Invited Paper) In Proceedings of WOFE, 2011.

Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography

Q. Zhu, L. Pileggi , F. Franchetti, “Cost-Effective Smart Memory Implementation for Parallel Backprojection in Computed Tomography”, VLSI-SoC, October 2012.

Statistical Design and Optimization for Adaptive Post-Silicon Tuning of MEMS Filters

F. Wang, G. Keskin, A. Phelps, J. Rotner, X. Li, G. Fedder, T. Mukherjee and L. Pileggi, “Statistical Design and Optimization for Adaptive Post-Silicon Tuning of MEMS Filters”, IEEE/ACM Design Automation Conference (DAC), 2012.