RC-Interconnect Macromodels for Timing Simulation
Florin Dartu, Bogdan Tutuianu and Lawrence T. Pileggi, “RC-Interconnect Macromodels for Timing Simulation”, Proceedings of the Design Automation Conference , 1996.
Archive for month: September, 1996
Modeling Signal Waveshapes for Empirical CMOS Gate Delay Models
/0 Comments/in Conference, Electronic Design Automation, Publications /by awpFlorentin Dartu and Lawrence T. Pileggi, “Modeling Signal Waveshapes for Empirical CMOS Gate Delay Models”, Sixth International Workshop on Power and Timing Modeling, Optimization and Simulation, September 1996.
Contact
Carnegie Mellon University
Hamerschlag Hall, 2113
5000 Forbes Avenue
Pittsburgh, PA 15213-3891 USA
pileggi@andrew.cmu.edu
Phone: 412-268-6774